Speaker
Description
The drive for higher spatial resolution and larger tracking coverage in high-energy physics has led to silicon pixel detectors spanning several square meters, integrating tens of thousands of readout units. Conventional parallel powering, which supplies each module via separate cables, results in a proliferation of cabling that dramatically increases the material budget, exacerbates multiple Coulomb scattering, degrades tracking performance, and introduces severe engineering challenges. To fundamentally reduce cable count and minimize material mass, serial powering—connecting multiple modules in series driven by a constant-current source—has emerged as a critical enabling technology. This approach reduces power cables from quadratic to linear scaling with the number of modules.
Although not yet used in operational experiments, serial powering has been adopted as the baseline architecture for the HL-LHC ATLAS ITkPixel and CMS Inner Tracker upgrades, with LHCb Upgrade II pursuing related R&D. Building on the LHCb roadmap, we are conducting domestic research using HV-CMOS pixel sensor chips. Our efforts focus on ATLASPix3-based Shunt-LDO (SLDO) tests, including probe card design, bare chip characterization, and PCB-level validation. Concurrently, we are evaluating COFFEE and CHiR chips with integrated SLDO designs. Future plans include probe card improvements to optimize load values and core chip connections, ATLASPix-based module prototyping using a 1×4 test board designed on a Quad flex (limited to fewer than nine chips), and CHiR-based tests upon chip availability. Through these systematic steps, serial powering demonstrates broad applicability and strategic importance for next-generation experiments, offering a critical solution to the material and complexity challenges of ultra-large-scale silicon tracking systems.
| Type of presentation (in-person/online) | Online presentation (Zoom) |
|---|