Speakers
Description
Autonomous radio detection of extensive air showers requires trigger decisions under non-stationary radio-frequency interference, limited bandwidth, and microsecond-scale latency. We present an FPGA-based hardware validation framework for a resource-efficient AI self-trigger aimed at station-level radio detectors. The system combines deterministic trace replay, controlled signal injection, buffering, metadata handling, and real-time trigger readout. The trigger under test is a compact fixed-point denoiser-classifier pipeline evaluated with detector-level air-shower radio signals embedded in measured background noise. Preliminary synthesis on a Xilinx Zynq-7000 indicates 42 DSPs, 22920 LUTs, 50 BRAMs, and about 1 W estimated power.
Summary (500 words)
Self-triggered radio detection is a major instrumentation challenge for astroparticle physics. Short radio pulses from extensive air showers must be identified in continuous background data that contain narrow-band transmitters, transient disturbances, and anthropogenic radio-frequency interference. Conventional threshold-based triggers therefore face a difficult trade-off: low thresholds lead to unsustainable trigger rates, while high thresholds suppress weak but physically relevant events. This contribution presents an FPGA-based hardware validation framework for studying AI-assisted station-level radio triggering under realistic detector conditions.
The system is developed around a compact AI trigger consisting of a waveform denoiser followed by a binary classifier. The trigger is designed for fixed-point FPGA implementation and is optimized with station-level constraints in mind: latency, resource use, power consumption, buffering, and stable continuous operation. The input data used for validation combine detector-level air-shower radio signals with measured ground-based background noise. This produces a controlled benchmark in which low-SNR air-shower-like pulses are embedded in realistic, non-stationary interference.
The main focus of the poster is the hardware validation chain rather than a finalized deployed trigger. The framework is based on deterministic trace replay: recorded traces are loaded into FPGA memory and passed through the processing chain in a reproducible way. This allows identical test vectors to be used for firmware debugging, latency studies, rate measurements, and comparison between trigger configurations. A shared Stage-0 input path performs buffering, window extraction, metadata handling, and forwarding of samples to the AI trigger.
This architecture is intended to close the gap between offline trigger studies and deployable station electronics. It allows controlled injection of simulated or recorded pulses into measured backgrounds, while preserving timing and dataflow constraints relevant for real-time operation. The validation framework can therefore be used to quantify latency, false-trigger rate, rate stability, and robustness against transient interference under reproducible hardware conditions.
Preliminary synthesis results for the current compact trigger design on a Xilinx Zynq-7000 device indicate a resource footprint of 42 DSPs, 22920 LUTs, 50 BRAMs, and about 1 W estimated power. Compared with earlier, less hardware-constrained implementations, this represents a substantial reduction in FPGA resource usage and opens a path toward compact, low-power station-level deployment. Trigger studies using the same benchmark indicate that the denoiser-classifier approach improves performance in the low-false-positive-rate regime compared with a classical peak-envelope threshold trigger, particularly for near-threshold signals.
The poster will present the validation architecture, deterministic replay input path, trigger firmware concept, preliminary FPGA resource estimates, and benchmark strategy. The work is directly relevant to programmable logic applications, trigger and data-acquisition systems, verification methods, and resource-constrained real-time electronics for particle and astroparticle physics.