28 September 2026 to 2 October 2026
Castelldefels, Barcelona, Spain
Europe/Zurich timezone

SEU characterization of a Low-Power 16 nm SRAM FPGA for On-Detector Intelligence

29 Sept 2026, 13:40
1h 40m
Castelldefels, Barcelona, Spain

Castelldefels, Barcelona, Spain

Hotel Rey Don Jaime
Poster Radiation - Radiation-Tolerant Components and Systems Poster 1

Speaker

Nour Sharif

Description

Modern low-power SRAM-based FPGAs such as the Efinix Ti60 FPGA, fabricated in 16 nm FinFET technology, are emerging as promising candidates for on-detector processing in high-energy physics. These devices offer compact form factor, low power consumption, and cost-efficient integration. However, their radiation tolerance and susceptibility to single-event upsets (SEUs) remain largely unexplored.

This work presents the first proton irradiation study of this device, using a dedicated setup enabling real-time monitoring and independent extraction of configuration and user logic SEU cross-sections. Mitigation techniques such as triple modular redundancy (TMR) are integrated to evaluate fault tolerance.

Summary (500 words)

The increasing demand for real-time data processing in high-energy physics has driven interest in deploying programmable logic directly at the detector level. Performing data processing close to the sensor enables early data reduction, feature extraction, and event filtering, thereby reducing data bandwidth and system latency. In this context, modern low-power SRAM-based FPGAs such as the Efinix Ti60, fabricated in 16 nm FinFET technology, are emerging as promising candidates due to their compact form factor, low power consumption, and cost-efficient integration.

A distinctive aspect of these devices is the proprietary Quantum™ compute fabric, which departs from conventional LUT-based FPGA architectures by employing a fine-grained, cell-based logic and routing structure. This architecture improves logic utilization and routing efficiency while reducing power consumption. Such characteristics are particularly advantageous for on-detector processing, where strict constraints on power, area, and thermal dissipation must be met. However, the radiation tolerance of this architecture, and in particular its susceptibility to single-event upsets (SEUs), remains largely unexplored.

This study presents the first proton irradiation characterization of the Efinix Ti60 FPGA, focusing on the evaluation of SEU sensitivity in both configuration memory and user logic. A dedicated experimental setup has been developed to enable controlled irradiation and continuous monitoring of the device under test. The setup allows real-time detection of upset events and supports independent extraction of SEU cross-sections without reliance on vendor-specific mitigation features, thereby providing direct insight into the intrinsic radiation response of the device.

The experimental campaign includes initial validation measurements using X-ray irradiation to verify the functionality of the test infrastructure and data acquisition chain. Proton irradiation tests are subsequently performed to induce SEUs under controlled conditions and to obtain statistically significant cross-section data. During these experiments, key operating parameters such as clock frequency, logic utilization, and configuration patterns are systematically varied to investigate their influence on upset rates.

The analysis focuses on identifying sensitive regions within the FPGA architecture, including configuration bits, flip-flops, and embedded memory elements. By correlating observed upset events with specific architectural resources, the study provides insight into how different components contribute to the overall radiation sensitivity. Particular attention is given to the impact of the distributed Quantum™ fabric on error localization and propagation, which may differ from conventional FPGA architectures.

To assess system-level robustness, mitigation techniques such as triple modular redundancy (TMR) are implemented and evaluated within the same experimental framework. Their effectiveness is analyzed in terms of error suppression capability, resource overhead, and impact on power consumption, enabling a direct comparison between protected and unprotected configurations under irradiation.

The results of this work contribute to a first characterization of SEU behavior in a modern low-power FPGA architecture and provide a basis for evaluating its suitability for use in radiation environments. If sufficient robustness can be demonstrated, such devices offer strong potential for enabling on-detector intelligence, supporting real-time data processing while reducing bandwidth requirements and improving overall system efficiency in next-generation high-energy physics experiments.

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