Speaker
Description
Summary
The jitter quality of the 40MHz Bunch Clock distributed to the front-end electronics of the LHC experiments is one of the most classical and polemical questions discussed within electronics and applied physics communities.
Jitter and phase-noise are indeed complex concepts, composed of numerous sub-categories which can variously impact different systems. Many papers already exist about these general notions. In the aim of helping experiments to better define their requirements on clock quality for the upgrades, this paper will deal with jitter and phase-noise, specifically applied to LHC bunch clock distribution system. In particular, it will try to answer questions like: which type of jitter and noise does affect which type of equipment (what is the impact of a cycle-to-cycle jitter or a TIE jitter on electronics)? Reciprocally, how does a constraint set by a precise, high speed ADC, a high speed transmission line, a detector resolution, result in term of jitter requirement? How does current legacy TTC system answer to these precise needs of experiments? Which performances could be reached by the various technical solutions investigated for upgrades? Finally, these values will be put into perspective by comparing them to the LHC beam characteristics (RF phase noise and phase fluctuations during ramp and flat top, longitudinal bunch profile variations, bunch oscillations and displacement, etc..).
