Dr
Todd Brian Huffman
(University of Oxford (GB))
9/17/12, 2:15 PM
Dr
John Wheater
(University of Oxford)
9/17/12, 2:30 PM
Dr
Frances Lannon
(Oxford University)
9/17/12, 3:00 PM
Lady Margaret Hall is one of thirty colleges in the University of Oxford that educate both undergraduate and graduate students. A further seven colleges are for graduates only, and one – All Souls – has only fellows.
Each college has its own history and style. LMH was founded in 1878 to enable women to study at Oxford for the first time. In 1978 it became co-educational. It has always...
Johan Fopma
(University of Oxford)
9/17/12, 3:20 PM
Oxford’s Department of Physics champions the notion that Physics Research needs strong technical support.
To this end it has around 40 staff providing Mechanical, Photo Fabrication and Electronics Engineering and related manufacturing support using a wide range of modern tools.
In recent years these services have been designated as cost recovered services allowing them to provide support for...
Mr
Marcus Julian French
(STFC - Science & Technology Facilities Council (GB))
9/17/12, 4:30 PM
The UK Science and Technology Facilities Council (STFC) provides electronics and instrumentation solutions to large scale scientific facilities in the UK and world-wide. The Technology Department of the STFC plays a leading role in developing, deploying and supporting the requirements of those facilities for advanced electronics and detectors. The talk will look at those facilities...
Peter Goettlicher
(Deutsches Elektronen-Synchrotron (DE))
9/17/12, 5:15 PM
For the scattering experiments of X-rays at FELS’s new instruments, cameras are currently being developed to record two dimensional images with increased picture rate and the feature to store scatterings of individual X-ray bunches on the targets. Combined with the very intense bunches of FEL’s this will allow to extract the structure of the target from scattering of individual bunches.
The...
Dr
Todd Brian Huffman
(University of Oxford (GB))
9/17/12, 6:00 PM
On July 4th of this year we all know what was dominating the Headlines. "Higgs boson-like discovery claimed at LHC" enthused the BBC. The New York Times was far more excited with the headline: "Physicists Find Elusive Particle Seen as Key to Universe". Many of us watched Fabiola Gianotti and Joe Incandela's talks on the discovery from ATLAS and CMS respectively and in the end saw many plots...
Prof.
David Richardson
(University of Southampton)
9/18/12, 9:00 AM
Using sun and reflectors, communicating with light goes back thousands of years. But with the advent of lasers and optical fibres in the later half of the past century a revolution occurred in the telecommunications industry. A single fibre made of a flexible strand of ultra-pure silica, with a width not much greater than that of a human hair, has the capacity to transmit more than 250 million...
Andrea Triossi
(Universita e INFN (IT))
9/18/12, 9:50 AM
Oral
With this work we want to demonstrate that an optical physical medium is compatible with the second generation of PCI Express. The benefit introduced by the optical decoupling of a PCI Express endpoint is twofold: it allows for a geographical detachment of the device and it remains compliant with the usual PCI accesses to the legacy I/O and memory spaces. We propose two boards, that can bridge...
Malte Backhaus
(Universitaet Bonn (DE))
9/18/12, 9:50 AM
Oral
A production run of FE-I4 pixel readout chips (denominated FE-I4B) was submitted September 2011 and first wafers were received in December. These chips are being used to build the Insertable B-Layer upgrade for ATLAS, to be installed during the 2013-14 shutdown. Results will be presented for detailed probing characterization of these wafers, as well as measurements of chips on boards before...
David Underwood
(Argonne National Laboratory (US))
9/18/12, 10:15 AM
Oral
Optical links will be an integral part of future HEP experiments at various scales from coupled sensors to off-detector communication. We are investigating light modulators as an alternative to VCSELs. Light modulators are small, use less power, have high bandwidth, are reliable, have low bit error rates and are very rad-hard. We present the quality of the links at 10GB/s and the results of...
Mohsine Menouni
(Centre National de la Recherche Scientifique (FR))
9/18/12, 10:15 AM
Oral
we have explored the use of the 65 nm CMOS technology node for pixel readout. A demonstrator 500-pixel matrix containing analog front ends only (no complex functionality), was designed and fabricated in Summer 2011, and irradiated with protons in Dec. 2011 and May 2012. We present the design and measurement results for this prototype.
Lawrence Soung Yee
(Universite catholique de Louvain)
9/18/12, 11:10 AM
Oral
A monolithic Active Pixel sensor for charged particle tracking has been developed. This sensor is within the frame of a R&D project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology), with the aim of studying the feasibility of developing a Monolithic Active Pixel Sensor (MAPS)with SOI technology. TRAPPISTe-2 is the second prototype in this series and was...
Tiankuan Liu
(Southern Methodist University)
9/18/12, 11:10 AM
Oral
We present the design of an optical link for the ATLAS liquid argon calorimeter upgrade. Challenging requirements are high data bandwidth (over 150 Gb/s raw data rate per board), radiation tolerance, low power consumption, high reliability, and low transmission latency. We discuss the link system design and component developments, especially those for the transmitting side that has to operate...
Dr
Jan Troska
(CERN)
9/18/12, 11:35 AM
Oral
We summarize the results obtained in a series of radiation tests of candidate laser and photodiode components for use in the Versatile Transceiver (VTRx), the front-end component of the Versatile Link. We have carried out radiation testing at a full spectrum of sources (neutrons, pions, gammas) and can now compare the results and show that the spectrum of components that meet the radiation...
Mikhail Lemarenko
(Universitaet Bonn (DE))
9/18/12, 12:00 PM
Oral
In the new Belle II detector, which is currently under construction at the Super-KEKB e+/e- collider, two additional pixel layers using the DEPFET technology will be introduced- to improve the vertex reconstruction in the high luminosity environment. The Data Handling Processor chip, which is directly bump bonded to the silicon of the DEPFET modules, is designed to steer the readout process,...
Dr
Jinyuan Wu
(Fermilab)
9/18/12, 2:50 PM
Oral
A digitization scheme of sub-microampere current using a commercial comparator with adjustable hysteresis and FPGA-based Wave Union TDC has been tested. The comparator plus a few passive components forms a current controlled oscillator and the input current is sent into the hysteresis control pin. The input current is converted into the transition times of the oscillations, which are...
Dr
Weiming Qian
(Rutherford Appleton Laboratory)
9/18/12, 3:14 PM
Oral
The ATLAS Level-1 Trigger requires several upgrades to maintain physics sensitivity as the LHC luminosity is raised. One of the most challenging is the electron trigger, with a major development planned for installation in 2018.
New on-detector electronics will be installed to digitise electromagnetic calorimetry signals, providing trigger access to shower profile information. The trigger...
Maximilian Buchele
(Albert-Ludwigs-Universitaet Freiburg (DE))
9/18/12, 3:15 PM
Oral
The GANDALF 6U-VME64x/VXS module has been developed to cope with a variety of readout tasks in nuclear physics experiments and is amongst others operated at the COMPASS experiment at CERN. Based on this platform, we present a 128-channel TDC which is implemented in a Xilinx Virtex-5 FPGA using the shifted-clock-sampling method. Compared to well-known FPGA designs based on delay-lines, usually...
Pamela Renee Klabbers
(University of Wisconsin (US))
9/18/12, 3:39 PM
Oral
As the LHC increases luminosity and energy, it will become increasingly difficult to select interesting physics events and remain within the readout bandwidth limitations. An upgrade to the CMS Calorimeter Trigger implementing more complex algorithms is proposed. It utilizes AMC cards with Xilinx FPGAs running in micro-TCA crate with card interconnections via crate backplanes and optical...
Steffen Staerz
(TU Dresden)
9/18/12, 3:40 PM
Oral
In the context of upgraded read-out systems for the Liquid-Argon Calorimeters of the ATLAS detector, modified front-end, back-end and trigger electronics are foreseen for operation at the High-Luminosity LHC. Accuracy and efficiency of the energy measurement and reliability of pile-up suppression are substantial when processing the detector raw-data in real-time. Several digital filter...
Dr
Michael Traxler
(GSI Helmholtz Centre for Heavy Ion Research)
9/18/12, 4:05 PM
Oral
One of the most important aspects of particle identification experiments is the digitisation of time, amplitude and charge data from detectors. These conversions are done mostly with Application Specific ICs (ASICs). However, the recent developments in Field Programmable Gate Array (FPGA) technology allow us to use commercial electronic components for the required Front-End Electronics (FEE)...
Datao Gong
(Southern Methodist Univeristy)
9/18/12, 5:00 PM
Poster
We present a high-speed, low power serializer ASIC, LOCs2, for the ATLAS liquid argon calorimeter upgrade. The ASIC consists of two 8 Gbps serializer channels, each of which has a 16-bit parallel data input in LVDS and a serial data output in CML logic. The ASIC is designed and fabricated in a 0.25-um commercial silicon-on-sapphire CMOS technology which is suitable for the high energy physics...
113.
An 8-channel Programmable 80/160/320 Mbit/s Radiation-Hard Phase-Aligner Circuit in 130 nm CMOS
Filip Francis Tavernier
(CERN)
9/18/12, 5:01 PM
Poster
The design of an 8-channel phase aligner is presented that is to be used in the GBTX chip for the LHC upgrade program. The circuit is able to align the phases of up to 8 parallel data streams to the GBTX transmitter clock so that the data can be serialized. The bit rate is programmable between 80, 160 or 320 Mbit/s. Data jitter up to ± 3•Tbit/8 can be tolerated without compromising the...
Dr
FREDERIC MOREL
(IPHC-UDS-IN2P-CNRS)
9/18/12, 5:02 PM
Poster
A 48 × 64 pixels prototype CMOS pixel sensor integrated with 4-bit column-level, self triggered ADCs for the ILD vertex detector outer layers was developed and fabricated in a 0.35 µm CMOS process with a pixel pitch of 35 µm. The pixel concept combines in-pixel amplification with a correlated double sampling operation. The ADCs accommodating the pixel read out in a rolling shutter mode...
Futian Liang
(University of Science and Technology of China; Southern Methodist University)
9/18/12, 5:03 PM
Poster
We present the design and the preliminary test results of LOCld1 and LOCld4, the VCSEL drivers fabricated in a commercial 0.25-um silicon-on-sapphire (SOS) CMOS process for the ATLAS liquid argon calorimeter upgrade. Because of the bandwidth limitation of the process, we use an active shunt peaking technique, multiple-stage amplification and a voltage higher than the nominal voltage to achieve...
Mr
Hans Kristian Soltveit
(Physikalisches Institut)
9/18/12, 5:04 PM
Poster
A Millimeter Wave Chip for a possible upgrade of the ATLAS Fast Tracker is under development. The 60 GHz unlicensed frequency band is of particular interest for indoor point-to-point multi gigabit data transfer due to its very large amount of spectral bandwidth (7-9 GHz). The targeted data rate for the first prototype is 3 Gbps. In this talk the key building blocks will be described, the...
Riccardo Travaglini
(Universita e INFN (IT))
9/18/12, 5:05 PM
Poster
The Insertable B-layer is planned for the upgrade of the ATLAS at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations...
Jan Scheirich
(Charles University (CZ))
9/18/12, 5:06 PM
Poster
DEPFET is an active pixel particle detector, in which a MOSFET is integrated in each pixel, providing first amplification stage of readout electronics. Excellent signal over noise performance is provided this way. The DEPFET sensor is planned to be used as an inner pixel detector in the BELLE II experiment at electron-positron SuperKEKB collider in Japan. Gated operation of the DEPFET is a...
Jim Hoff
(Fermilab)
9/18/12, 5:07 PM
Poster
Future LHC experiments demand greater speed and orders of magnitude more patterns from associative memory-based track finders. The scaling of current technology in 2D is unlikely to satisfy the scientific needs. New technology will be needed. 3D Vertical Integration not only provides more active silicon per unit area creating higher pattern density, but also permits geometrical...
Simone Esch
(IKP, Forschungszentrum Jülich)
9/18/12, 5:08 PM
Poster
The Micro Vertex Detector (MVD) is the innermost tracking detector of the PANDA experiment at the upcoming FAIR facility in Darmstadt. The detector consists of several layers of silicon pixel and strip sensors to obtain precise tracking of charged particles.
For the development of a front-end ASIC a flexible and powerful readout system was developed to interface different ASIC prototypes.
We...
Marius Wensing
(Bergische Universitaet Wuppertal (DE))
9/18/12, 5:09 PM
Poster
For the coming upgrade of the ATLAS pixel detector at CERN a redesign of the current data readout is necessary. To communicate with the additional 448 front-end chips assembled in the Insertable B-Layer (IBL) new FPGA readout cards consisting of a Back of Crate card (BOC) and a Read Out Driver (ROD) have been developed. This paper will describe the firmware and hardware development of the new...
Dr
Tiankuan Liu
(Southern Methodist University)
9/18/12, 5:10 PM
Poster
We propose a line code for the optical data links of the ATLAS liquid argon calorimeter upgrade. The line encoder inserts a frame trailer at the end of each data frame before the data are scrambled and the line decoder recovers the beginning and end of each frame, descrambles the data frame, and removes the frame trailer. The line code has low latency, low overhead, fast resynchronization...
Dr
Paschalis Vichoudis
(CERN)
9/18/12, 5:18 PM
Poster
The Gigabit Link Interface Board (GLIB) project is an FPGA-based platform for users of high-speed optical links in high energy physics experiments. The major hardware component is the GLIB Advanced Mezzanine Card (AMC). Additionally to the GLIB AMC, auxiliary add-on boards are under development in order to enhance the GLIB AMC I/O bandwidth and compatibility with legacy and future triggering...
Lauri Juhani Olantera
(CERN)
9/18/12, 5:19 PM
Poster
The Versatile Transceiver is a part of the Versatile Link project, which is developing optical link architectures and components for future HL-LHC experiments. While having considerable size and weight constraints Versatile Transceivers must work in severe environmental conditions. One such environmental parameter is the temperature: the operating temperature range is specified to be from -30...
Mr
Mikhail Matveev
(Rice University)
9/18/12, 5:20 PM
Poster
We present the results of initial tests of prototype optical links of an upgraded trigger for the Cathode Strip Chamber sub-detector at the CMS experiment at CERN. After presenting an overview of the existing system and upgrade requirements, we describe the hardware and firmware developed to drive the new links.
Results of initial tests with the prototype Track Finder board and...
Deepak Gajanana
(NIKHEF)
9/18/12, 5:21 PM
Poster
Particle detectors in High Energy Physics experiments, contain various types circuits and demand data rates of multiple Gbps per chip and several Tbps for the whole detector. Optical transmission by external modulation of a continuous wave laser is a possible solution to tackle the problem of high data rates.In this paper, we investigate the radiation hardness performance of InP-based...
Alvaro Navarro Tobar
(Centro de Investigaciones Energ. Medioambientales y Tecn. - (ES)
9/18/12, 5:22 PM
Poster
CMS DT electronics upgrade involves laying down 3500 optical links from the CMS cavern to the counting room, whose lengths must be matched to minimize skew, so that the present upstream electronics can be reused at an initial stage. In order to assess the cables’ compliance, a high resolution and cost-effective system has been developed to measure the length uniformity of these fibres....
Paolo De Remigis
(INFN sez. di Torino)
9/18/12, 5:23 PM
Poster
The upgrade of the Drift Tube system of the CMS experiment foresees the relocation of the Sector Collector from the cavern to the counting room. It is thus required to convert the signals from electrical to optical, for a total number of 3500 channels running up to 480 Mb/s. A Copper to Optical Fiber (CuOF) board is currently under design. The board is divided into a mother board, which hosts...
annie xiang
(Southern Methodist University)
9/18/12, 5:24 PM
Poster
The 120Gbps optical transmitter is a 12-channel, 10Gbps per channel, parallel pluggable module to operate on the detector front-end for the readout and control of High-Luminosity LHC (HL-LHC) experiments. We present the design concepts based on multiple TOSAs, precision array coupling and drop-in opto engines. We describe the prototype development and the experimental set-up for parametric...
Giovanni Mazza
(INFN sez. di Torino)
9/18/12, 5:31 PM
Poster
The readout architecture for the silicon pixel sensors of the PANDA MVD is presented.The pixel detector has to provide timing, position and energy information on a event-driven base, since no trigger signal is foreseen.
The readout system is based on a custom ASIC, named ToPiX, directly connected to the GBT optical transceiver. A reduced size prototype with most of the main functionality has...
Mr
Alan Prosser
(Fermilab)
9/18/12, 5:32 PM
Poster
We have designed an advanced test-beam facility including a pixel tracking telescope. In the data path between the telescope and a PC, a commercial MicroTCA crate houses an Advanced Mezzanine Card (AMC) which receives, buffers, and processes the data from the tracking telescope, transmitting complete assembled events to the PC in real-time. This approach makes possible rapid assessment of the...
Steven Welch
(Oklahoma State University (US))
9/18/12, 5:33 PM
Poster
The ATLAS Pixel new Service Quarter Panel (nSQP) project aims to deliver replacements for all on-detector services of the ATLAS Pixel Detector. The nSQPs will have LVDS transceivers at the place of the present electro-optical converters. The transceivers, realized in 130 nm technology, communicate with the existing ATLAS Pixel MCC chips, and over a 6.6m long electrical transmission line with...
Ms
Sandra Saornil Gamarra
(Universitaet Zuerich (CH) on behalf of LHCb Silicon Tracker group)
9/18/12, 5:34 PM
Poster
The LHCb Silicon Tracker is part of the main tracking system of the LHCb detector at the LHC. It measures very precisely the particle trajectories coming from the interaction point in the region of high occupancies around the beam axis.
After presenting our production and comissioning issues in TWEPP 2008, we report on our running experience. Focusing on electronic and hardware issues as...
Sam Cook
(University College London)
9/18/12, 5:35 PM
Poster
The clock and control (CC) system for the EuXFEL megapixel detectors was presented in TWEPP 2011. It consists of a multipurpose MTCA.4 AMC card with an FPGA and a custom designed Rear Transition Module (RTM). This paper presents the experiences with the system since its first prototype and the development of the final hardware. Experiences with the hardware included the tests performed to...
Mr
Robert Schnell
(HISKP, University Bonn; II. Phys. Inst., University Giessen)
9/18/12, 5:36 PM
Poster
The PANDA experiment at the future FAIR facility will study annihilation reactions of antiprotons. The Micro-Vertex-Detector as part of the tracking system will permit precise tracking and detection of secondary vertices. It is made of silicon pixel detectors and double-sided silicon strip detectors.
Aspects of the development for the strip detector will be presented: Evaluation of prototype...
Janos Ero
(Austrian Academy of Sciences (AT))
9/18/12, 5:43 PM
Poster
The upgrade of the Drift Tube Track Finder (DTTF) electronics will be designed using VHDL synthesis. The construction of the HDL structure merges improved blocks of the Track Finding algorithms and the results of the CMS wide detector control, monitoring and DAQ output common development. This merged design is subject of extended simulations both on behavioral level and concerning the timing...
Volker Wenzel
(Johannes-Gutenberg-Universitaet Mainz (DE))
9/18/12, 5:44 PM
Poster
By 2014 the LHC will collide proton bunches at 14 TeV with an increased instantaneous luminosity up to 3×10^34cm−2s−1. A reduction on the trigger rate can be achieved by applying topological cuts adopting a new FPGA based module in the L1 trigger: the Topological Processor (TP). This presentation focuses on the design of the first TP prototype and on the test results on algorithm implemented...
Ben Cooper
(University College London)
9/18/12, 5:45 PM
Poster
The increased collision rate and pile-up produced at the HLLHC requires a substantial upgrade of the ATLAS level-1 trigger in order to maintain a broad physics reach. We show that tracking information can be used to control trigger rates, and describe a proposal for how this information can be extracted within a two-stage level-1 trigger design that has become the baseline for the HLLHC...
Victor Andrei
(Ruprecht-Karls-Universitaet Heidelberg (DE))
9/18/12, 5:46 PM
Poster
The ATLAS Level-1 Calorimeter Trigger is a pipelined system to identify high-pT objects and to build energy sums within a fixed latency of ~2 us. It consists of a PreProcessor, which conditions and digitises analogue calorimeter signals, and two object-finding processors. The PreProcessor's tasks are implemented on a Multi-Chip Module, holding ADCs, time-adjustment and digital processing...
Mr
Raul Esteve
(Universitat Politècnica de València)
9/18/12, 5:47 PM
Poster
NEXT-DEMO is a large-scale prototype of NEXT, an experiment to search for neutrinoless double beta decays using a radiopure high-pressure gaseous xenon TPC with electroluminescence readout. Based on a PMT plane for energy measurements and a SiPM tracking plane for topological event filtering, front-end electronics, trigger and data-acquisition systems (DAQ) have been built. The DAQ is a...
Mr
Jose Carlos Da SIlva
(LIP LISBON)
9/18/12, 5:48 PM
Poster
The calorimeter trigger synchronization of the Compact Muon Solenoid experiment at the large hadron collider (LHC) uses a synchronization method implemented in the synchronization and link board (SLB). The board allows the synchronization of electromagnetic and hadronic trigger primitives at the LHC frequency (40.08 MHz) and its transmission to the Regional Calorimeter Trigger. The new...
Dr
Andrew William Rose
(Imperial College Sci., Tech. & Med. (GB))
9/18/12, 5:49 PM
Poster
Test results are presented for two AMC cards, the "CTP6" and "MP7", along with results from a custom Vadatech VT893 backplane. The two cards take different approaches to connectivity: one with fully-populated backplane connectivity and a 396Gbps asymmetric, optical interface, the other favouring, instead, a 1.4Tbps, symmetric, all-optical interface. The challenges of designing these cards...
Dr
Alfons Weber
(STFC/RAL)
9/19/12, 9:00 AM
Large non-collider experiments have special requirements for their electronics. Especially neutrino experiments have a large number of channels to read out the largest possible detector volume. The price per channel is often one of the design drivers, while at the same time having no dead time and 100% efficiency for the rare signal events. Data volume for these experiments is also often...
Mr
Gianluca Furano
(European Space Agency)
9/19/12, 9:45 AM
Oral
Many R&D activities are ongoing at European Space Agency to secure European industries competitiveness and non-dependence especially for what concerns EEE parts and avionics systems.
Many synergies with experiences in astroparticle physics and in accelerator experiments exists, and will be presented and discussed.
Future ESA flagship science mission targets the demanding Jupiter orbit, where...
Dr
Markus Friedl
(Austrian Academy of Sciences (AT))
9/19/12, 9:45 AM
Oral
The Silicon Vertex Detector of the future Belle II experiment at KEK (Japan) will consist of 6” double-sided sensors. Those are read out by APV25 chips (originally developed for CMS) which are powered by DC/DC converters with floating low voltages on top of the bias potentials. The signals are transmitted by cable links of about 12 meters. In the back-end, the data are digitized and processed...
Daniel Muenstermann
(CERN)
9/19/12, 10:10 AM
Oral
We explore the concept of using a deep-submicron HV CMOS process to produce a drop-in replacement for traditional radiation-hard silicon sensors. Such active sensors contain simple circuits, e.g. amplifiers and discriminators, but still require a traditional (pixel or strip) readout chip. This approach yields most advantages of MAPS (improved resolution, reduced cost and material budget,...
Andrea Boccardi
(CERN)
9/19/12, 10:10 AM
Oral
The Beam Instrumentation Group (BI) is responsible for designing, building and maintaining the instruments that allow observation of the particle beams and the measurement of related parameters for all CERN accelerators and transfer lines. This contribution is aimed to give an overview of the ongoing electronic developments within the beam instrumentation group both to improve the performances...
Mrs
Sophie Baron
(CERN)
9/19/12, 11:10 AM
Oral
The quality of the 40MHz Bunch Clock distributed to the front-end electronics of the LHC experiments is one of the most classical questions discussed within electronics and applied physics communities.
Jitter and phase-noise are complex concepts, composed of numerous sub-categories which can variously impact systems. This paper will deal with jitter and phase-noise, specifically applied to...
Prof.
Kock Kiam Gan
(Ohio State University (US))
9/19/12, 11:10 AM
Oral
We designed two optical-link ASICs for a new pixel layer of ATLAS. The ASICs include a 5 Gb/s driver for a 12-channel VCSEL array and a receiver/decoder to extract the data and clock from a 12-channel PIN array. The performance of the ASICs is satisfactory, including the ability to bypass broken PIN/VCSELs and set the ASICs to a default configuration with a power-on reset circuits in an event...
Jens Verbeeck
(K.U. LEUVEN)
9/19/12, 11:35 AM
Oral
A chip is developed in a 130nm technology, containing a transimpedance amplifier with a 405MHz bandwidth, 89dBΩ transimpedance gain and a dynamic input range of 1:1600 for a photodiode capacitance of 0.75pF. The equivalent input noise is 216nA. The gain of the voltage amplifier, used in the TIA, degrades less than 3% over a temperature range from −40°C up to 125°C. The transimpedance-bandwidth...
47.
The AMC13 Module: A Common Solution for Clock, Controls and DAQ Services in CMS MicroTCA Systems
Eric Shearer Hazen
(Boston University (US))
9/19/12, 11:35 AM
Oral
We have developed a custom MicroTCA module which provides timing, control, trigger and data acquisition functions in a MicroTCA crate for CMS experiment upgrades. This module mounts in the redundant MCH slot in a MicroTCA crate, and distributes LHC RF clock and encoded fast timing signals to 12 AMC modules. Data are collected from AMC modules using a MicroTCA fabric and transmitted to the CMS...
Jean-Pierre Cachemiche
(Universite d'Aix - Marseille II (FR))
9/19/12, 12:00 PM
Oral
The LHCb collaboration has chosen to evaluate the ATCA architecture as form-factor for the LHCb readout system. A same board can satisfy all the requirements for data transmission, timing and fast control as well as slow control. First developments rely on a generic ATCA carrier board equipped with four dense AMC mezzanine able to interface a total of 144 bidirectional optical links at up to...
Giovanni Mazza
(INFN sez. di Torino, Italy)
9/19/12, 12:00 PM
Oral
The GigaBit Laser Driver (GBLD) is a radiation tolerant ASIC which is part of the GigaBit Transceiver (GBT) chip-set. It is aimed to drive both edge emitting and VCSEL laser diodes at a data rate in excess of 5 Gb/s. The GBLD can provide a modulation current up to 24 mA and a bias current up to 43 mA.Pre- and de-emphasis functions are implemented to compensate for high external capacitive...
David Stoppa
(Fondazione Bruno Kessler – FBK)
9/19/12, 2:00 PM
The impressive advancements in CMOS technologies over the last few decades have resulted in image sensors being a ubiquitous part of everyday life. However, there are always new challenges keeping research alive in the field of solid-state image sensors, with an increasing demand for imaging systems able to provide extra-information with respect to the standard digital cameras output. Among...
James David Degenhardt
(University of Pennsylvania (US))
9/19/12, 2:50 PM
Oral
The ATLAS Transition Radiation Tracker (TRT) is the outermost of the three subsystems of the ATLAS Inner Detector. ATLAS is one of two general‐purpose detectors built for the Large Hadron Collider at CERN. The TRT front‐end electronics use two custom‐built, radiation‐hard ASICs: the analog Amplifier, Shaper, Discriminator, Baseline Restorer (ASDBLR) chip and the Digital Time Measurement,...
Mr
Christian Irmler
(HEPHY Vienna)
9/19/12, 2:50 PM
Oral
The Belle II SVD will consist of four layers of double-sided silicon detectors, arranged in ladders. Each sensor will be read out individually by utilizing the Origami chip-on-sensor concept, where the APV25 chips are placed on flexible circuits, glued on top of the sensors. Beside a best compromise between low material budget and sufficient SNR, this concept allows efficient CO2 cooling of...
Giuseppe Guido Venturini
(Ecole Polytechnique Federale de Lausanne (CH))
9/19/12, 3:15 PM
Oral
The design is based on charge-to-frequency conversion, with the addition of a new system to reconfigure the front-end - depending on the input signal level to increase the dynamic range at constant sampling frequency. The ASIC has been designed in 0.25 μm radiation tolerant CMOS technology aiming to cover a dynamic range of six decades with a 25kHz sampling rate: design, simulation and...
Jan Michel
(Goethe University Frankfurt)
9/19/12, 3:15 PM
Oral
Many modern DAQ systems deploy a network running a custom network protocol to connect many FPGAs distributed on the detector. Key aspects are low latency, high bandwidth and also fault-tolerance. Another aspect is the control and monitoring system for the full detector. For the HADES experiment, the TrbNet protocol was developed to meet all of these requirements. The complete system is...
Filip Francis Tavernier
(CERN)
9/19/12, 3:40 PM
Oral
A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320 MHz as a reference and generates clocks at the same frequencies, regardless of the input. Moreover, the outputs are available with a phase resolution of 90° for the 40, 80 and 160 MHz output and 22.5° for the 320 MHz output. The radiation-hard design, integrated in a 130 nm CMOS...
Jan Troska
(CERN, Geneva, Switzerland)
9/19/12, 4:35 PM
Eric Shearer Hazen
(Boston University (US))
9/19/12, 4:40 PM
Sandro Bonacini
(CERN)
9/19/12, 4:45 PM
Peter Phillips
(STFC - Science & Technology Facilities Council (GB))
9/19/12, 4:45 PM
Anthony Weidberg
(University of Oxford (GB))
9/19/12, 5:05 PM
Jean-Pierre Cachemiche
(Universite d'Aix - Marseille II (FR))
9/19/12, 5:10 PM
Peter Goettlicher
(Deutsches Elektronen-Synchrotron (DE))
9/19/12, 5:30 PM
Annie Chu Xiang
(Southern Methodist University (SMU))
9/19/12, 5:35 PM
Sorin Martoiu
(Horia Hulubei National Institute of Physics and Nuclear Enginee)
9/19/12, 5:45 PM
Prof.
Kock Kiam Gan
(Ohio State University (US))
9/19/12, 6:05 PM
Giovanni Ambrosi
(Universita e INFN (IT))
9/20/12, 9:00 AM
The Alpha Magnetic Spectrometer (AMS-02) is a high-energy physics experiment designed to operate in space on board the International Space Station (ISS), where it has been installed on May 16th 2011, and is taking data continuously since then. Thanks to the very large acceptance (~ 0.5 m2 sr) and an exposure time of several years, AMS-02 will measure a wealth of data to study with...
Ms
Sylvie BLIN
(Laboratoire de l'Accélérateur Linéaire)
9/20/12, 9:50 AM
Oral
The SPACIROC ASIC family is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). This rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which will equip the detection surface. Two main features of this ASIC are the photon counting mode for each input and the charge-to-time conversion for the multiplexed channels....
Sorin Martoiu
(Horia Hulubei National Institute of Physics and Nuclear Enginee)
9/20/12, 10:15 AM
Oral
Developed within RD51 Collaboration for the Development of Micro-Pattern Gas Detectors Technologies, the Scalable Readout System (SRS) is intended as a general purpose multi-channel readout solution for a wide range of detector types and detector complexities. The scalable architecture, achieved using multi-Gbps point-to-point links with no buses involved, allows the user to integrate...
Dr
Esko Mikkola
(Ridgetop Group, Inc.)
9/20/12, 10:15 AM
Oral
Radiation hardened analog to digital converter (ADC) has been designed for future high energy physics experiments. The ADC has been designed in a commercial 130nm CMOS process and it achieves 12-bit resolution,40 MS/s sampling speed, 15 mW power consumption and hardness to at least 1 Megarad(Si) of total ionizing dose (TID). 16 ADC channels will be placed on one packaged silicon chip. The ADC...
John Coughlan
(STFC - Science & Technology Facilities Council (GB))
9/20/12, 11:10 AM
Oral
The TrainBuilder is an Advanced Telecom ATCA data acquisition board being developed at the STFC Rutherford Appleton Laboratory to provide readout for the large 2D Mega-pixel detectors under construction for the European-XFEL in Hamburg. Each ATCA board can process ~8 GBytes/sec of raw detector data. The Train Builder system merges up to 5,120 partial detector images per second using FPGAs with...
Gianluigi De Geronimo
(Brookhaven National Laboratory)
9/20/12, 11:10 AM
Oral
We present a 64-channel ASIC designed for micropattern detectors. The ASIC discriminates and measures the amplitude and timing of events, including sub-threshold neighbors. With 200 pF input capacitance it provides charge resolution <5,000 electrons and sub-nanosecond timing resolution at 25 ns. The shaper, based on the concept of delayed dissipative feedback, gives an analog dynamic range in...
Mr
Laurent Royer
(IN2P3/Pôle MicRhau)
9/20/12, 11:35 AM
Oral
A readout chip has been developed to fulfil the requirements of the Si-W electromagnetic calorimeter of ILC. This electronics performs the complete processing of the signal: charge-sensitive amplification, synchronous shaping, analog memorization and digitization. Measurements show a global non-linearity better than 0.2% for low energy particles, and limited to 2% for high energy particles....
Oliver Grimm
(ETH Zürich)
9/20/12, 11:35 AM
Oral
The front-end electronics design and interface to the data processing unit of the STIX X-ray spectrometer on the ESA Solar Orbiter satellite is presented. Solar Orbiter will be launched in 2017 to study sun/heliosphere interactions. STIX detects X-rays with Cadmium Telluride crystals in the energy range 4-150 keV. An ASIC (IdeF-X HD) with separate ADC is used for read-out. To achieve 1 keV...
Dominik Fehlker
(University of Bergen (NO))
9/20/12, 12:00 PM
Oral
A prototype of a highly segmented electromagnetic calorimeter has been developed. The detector tower is made of 24 layers of PHASE2/MIMOSA23 silicon sensors sandwiched between tungsten plates, with 4 sensors per layer, resulting in 39 MPixels in total. A detector readout and control system was developed, containing two Spartan 6 and one Virtex 6 FPGA, and running embedded Linux. In 550 ms 4...
Peter Wieczorek
(GSI Darmstadt, Germany)
9/20/12, 12:00 PM
Oral
The ASIC design group at GSI developed a preamplifier and shaper ASIC which is optimized for the requirements of the electromagnetic calorimeter of the PANDA experiment. This integrated circuit will be used for spectroscopy and was designed for the readout of a large area APDs with 300pF detector capacitance, a very high dynamic range and an event rate of 350kHz. Each ASIC includes 2...
Mr
Thomas Toifl
(IBM Zurich)
9/20/12, 2:00 PM
Due to the ever-increasing number of transistors on a processor chip, I/Os are more and more becoming the limiting factor on system performance. This presentation will describe the challenges for implementing the physical layer of high-speed wireline I/Os in CMOS in order to achieve both high data throughput and low power consumption. We will discuss how these goals can be met by proper choice...
Stefan Huber
(Technische Universitaet Muenchen (DE))
9/20/12, 2:49 PM
Oral
In 2009 COMPASS performed a test measurement of neutral Primakoff reactions, characterized by high energetic photons in one of the two electromagnetic calorimeters. Back then a digital trigger had been implemented to the existing readout electronics in order to detect these events. For 2012 a long measurement of these processes is foreseen. In order to extend the cinematic range to lower...
Stefano Michelis
(CERN)
9/20/12, 2:50 PM
Oral
A new and complete DCDC converter ASIC prototype has been designed and manufactured in a commercial 0.35um CMOS technology. The circuit is aimed at applications in LHC upgrades, where it can function in the intense magnetic field and survive to the radiation environment of even the trackers. Rated for an input voltage up to 10V, it provides a selectable output voltage and embeds under-voltage,...
Prof.
Valentino Liberali
(Università degli Studi di Milano)
9/20/12, 3:14 PM
Oral
Modern experiments at hadron colliders search for extremely rare processes hidden in much larger background levels. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. The FastTracker (FTK) processor for the Atlas experiment offers extremely powerful, very compact and low power consumption processing units...
Gary Drake
(Argonne National Laboratory)
9/20/12, 3:15 PM
Oral
We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS Hadron Tile Calorimeter. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features. We discuss the steps taken to improve the design. We present the...
Olivier Raymond Bourrion
(Centre National de la Recherche Scientifique (FR))
9/20/12, 3:39 PM
Oral
The ALICE experiment at the LHC is equipped with an electromagnetic calorimeter (EMCal) designed to enhance its capabilities for jet measurement. In addition, the EMCal enables fast triggering on high energy jets and high pt photons with a multiplicity dependent threshold. After its commissioning in 2010, the EMCal L1 trigger has been officially approved for physics data taking in 2011....
Katja Klein
(Rheinisch-Westfaelische Tech. Hoch. (DE))
9/20/12, 3:40 PM
Oral
CMS has adapted a DC-DC conversion powering scheme for its phase-1 pixel upgrade, to be able to deliver the required amount of power with the existing cable plant.
The presentation will focus on aspects that are relevant for the integration of DC-DC buck converters into a detector system. New measurements based on a full-scale prototype ASIC (AMIS4, CERN PH-ESE) will be presented,...
Andrea Salamon
(INFN Sezione di Roma Tor Vergata)
9/20/12, 4:04 PM
Oral
The NA62 experiment at the CERN SPS aims to measure the Branching Ratio of the very rare kaon decay K+ -> pi+ nu nubar collecting ~100 events with a 10% background in two years of data taking. To reject the K+ -> pi+ pi0 background the NA48 liquid krypton calorimeter will be used in the 1-10 mrad angular region. A vertical slice of the trigger processor has been assembled and tested in the...
Peter Goettlicher
(Deutsches Elektronen-Synchrotron (DE))
9/20/12, 4:05 PM
Oral
To build homogeneous high granularity calorimeters low power consumption per channel is essential. Linear e+e- collider design duty cycles foresee bunch delivery over short periods, 1ms, followed by long, 200ms, breaks. Power cycling frontend electronics can reduce power consumption by a factor 100. For a full scale CALICE-AHCAL switched currents reach kilo Amperes magnitudes.
This talk...
Deepak Gajanana
(NIKHEF)
9/20/12, 5:00 PM
Poster
In the KM3NeT project, the electronics required to control the PMTs and collect the signals is integrated in two ASICs: 1. Front-end mixed signal ASIC (PROMiS) and 2. Analog ASIC (CoCo) to control the feedback of the high voltage (HV) circuit. We discuss the two integrated circuits and their test results. The read out ASIC amplifies converts input charge to pulse width and delivers the...
Alessandro Gabrielli
(Universita e INFN (IT))
9/20/12, 5:01 PM
Poster
We describe the design of a floating gate-based MOS sensor embedded in a read-out CMOS sensing element used as a radiation sensor. A maximum sensitivity of 1mV/rad is estimated up to 10krad. The paper shows the design of a microelectronic circuit that includes a sensor, an oscillator and modulator, which is now under fabrication. Given the small estimated area of the complete chip prototype,...
Selma Conforti Di Lorenzo
(OMEGA/LAL/IN2P3/CNRS)
9/20/12, 5:02 PM
Poster
The SPIROC chip is a dedicated very front-end electronics to read out a prototype of the Analog Hadronic Calorimeter (AHCAL) equipped with Silicon Photomultiplier (SiPM) for ILC (International Linear Collider).
A first prototype of SPIROC has been fabricated in 2007 and a second version in 2010. Many testbench and testbeam measurements have been performed showing a good overall behaviour....
Mr
Shiming Deng
(IPNL)
9/20/12, 5:03 PM
Poster
For developing a scintillating-fiber beam monitor, we have designed a front-end 16-Channels readout chip to be associated with PMTs in a 0.35 µm BiCMOS process. Each channel consists of one input current conveyor driving separately a current comparator for signal event detection and a charge-sensitive amplifier for signal charge measurement. The ASIC version 2 has brought significant...
Claudio Gotti
(University of Firenze and INFN Milano Bicocca)
9/20/12, 5:05 PM
Poster
An ASIC named CLARO-CMOS was designed for fast photon counting with MaPMTs, MCPs and SiPMs. The ASIC was realized in a .35 um CMOS technology, and has 4 channels, each with a fast amplifier and a discriminator. The main features of the design are the high speed of operation, aiming to completely eliminate the dead time at a 40 MHz event rate, and low power dissipation, around 1 mW/ch and...
Albert Comerma Montells
(Universidad de Barcelona)
9/20/12, 5:06 PM
Poster
A Front End ASIC for the readout of Silicon Photo-Multipliers is presented with the following features:
wide dynamic range, high speed, multi channel, low input impedance current preamplifier, low power (7mW per channel), DC coupled input with common mode voltage control and separated timing and charge signal output.
A detailed description of the SiPM modeling and parameter extraction is...
Edgar Lemos Cid
(Universidade de Santiago de Compostela (ES))
9/20/12, 5:13 PM
Poster
The goal of this project is to examine the feasibility of data transmission up to ~5Gbit/s on a short (~60cm) low mass flex cable. These cables will be used for the readout of the upgraded vertex detector (VELO) of the LHCb experiment in high radiation and vacuum environment. We present a study of different transmission line geometries, the effect of using fine pitch (400μm) connectors, the...
Georges Blanchot
(CERN)
9/20/12, 5:14 PM
Poster
The upgrade of the CMS tracker at the HL-LHC requires the design of new front-end modules to cope with the increased luminosity and to implement L1 trigger functionnality. The new modules under development are based on high density hybrid circuits with new flip-chip front-end ASIC, and are wire bonded to strip sensors and connected to a service board for the data transmission. The suitability...
Alessandro Mapelli
(CERN)
9/20/12, 5:15 PM
Poster
Microchannel cooling has been selected for the thermal management of the NA62 GTK detector. The baseline design is based on a 130 micron thick silicon microstructured plate spanning over the whole sensor surface. An alternative design, based on a "frame-like" geometry, is also under study. Experimental measurements detailing the performance of both configurations will be presented and...
Dr
Paschalis Vichoudis
(CERN)
9/20/12, 5:22 PM
Poster
In March 2012 the high voltage system of the silicon-sensor-based CMS Preshower detector underwent a significant upgrade. In addition to a doubling of the number of power supplies, a new active distribution board was developed and installed. This new board provides much improved flexibility in the powering, necessary to cope with the expected evolution of the 4288 silicon sensors with...
Peter Phillips
(STFC - Science & Technology Facilities Council (GB))
9/20/12, 5:23 PM
Poster
The engineering challenges related to the supply of electrical power to future large scale detector systems are well documented. The ATLAS Upgrade Strip Tracker Community has previously presented results from two demonstrator stavelets, one serially powered and one built with DC-DC convertors. Both approaches have the potential to increase the efficiency of the powering system.
At the time...
Alessandro Bartoloni
(Universita e INFN, Roma I (IT))
9/20/12, 5:24 PM
Poster
The CMS electro-magnetic calorimeter comprises 75848 scintillating lead tungstate crystals. 61200 crystals are contained in the ECAL Barrel section and these are readout by avalanche photodiodes (APD) with internal gain. The APD gain strongly depends on the bias voltage that, for a gain G=50, is around 400 V. In order to match the requirements for gain stability, the power supply voltage must...
Michal Bochenek
(University of Pennsylvania (US))
9/20/12, 5:25 PM
Poster
The power distribution systems in the ATLAS Inner Tracker Upgrade require linear voltage regulators on the front-end chips to be the last stages of the powering chain. In the paper we present two designs: a classical voltage regulator based on an NMOS transistor as the pass element and an LDO voltage regulator employing a PMOS device. Both prototype regulators have been implemented in the...
Maria Cristina Esteban Lallana
(Aragon Institute of Technology (ES))
9/20/12, 5:26 PM
Poster
The next generation of CMS tracker system will have all DC-DC converters located inside the tracker volume.They will be connected together in each rod via common power network, which propagates this noise along the rod.This paper presents several conducted and radiated test results on a prototype of the Pt power network.Test results will show the implication of the DC-DC converter position and...
Cristian Alejandro Fuentes Rojas
(CERN)
9/20/12, 5:27 PM
Poster
The precision requirements of the vertex detector at CLIC impose strong limitations on the mass of such a detector (<0.2 X0 per layer). To achieve such a low mass, ultra-thin hybrid pixel detectors are foreseen, while the mass for cooling and services will be reduced by implementing a power-pulsing scheme that uses the low duty cycle of the accelerator. The principal aim is to achieve...
Jennifer Jentzsch
(Technische Universitaet Dortmund (DE))
9/20/12, 5:34 PM
Poster
For the first ATLAS pixel upgrade scheduled in 2013 a new front-end chip generation (FE-I4) has been developed. The second version (FE-I4B) hosting two different solid-state sensor technologies (planar silicon and 3D silicon) has been produced to be built into a new pixel layer (the Insertable B-Layer, IBL). Prototypes of these assembled modules have been tested in laboratory and testbeam...
Pablo Moreno
(Universidad de Valencia)
9/20/12, 5:35 PM
Poster
This paper describes a new portable test bench for the TileCal sub-detector of the ATLAS experiment at CERN. The system is used for the certification and quality checks of the front-end electronics drawers. It is designed to be an easily upgradable version of the current 10-year-old system, able to evaluate the new technologies planned for the upgrade as well as provide new functionality to...
Vladimir Zivkovic
(NIKHEF Institute)
9/20/12, 5:36 PM
Poster
The article addresses production test development effort of the ATLAS FE-I4 integrated circuit. This particular production test targets manufacturing faults in the ICs and has been taken as a supplementary approach, besides standard functional test, to decrease further the risk of potential application failures. The Design-for-Test structures inside the digital part of the chip together with...
58.
New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC
Lukas Püllen
(Uni-Wuppertal)
9/20/12, 5:43 PM
Poster
In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled. In this upgrade, the inner detector of the ATLAS experiment will be replaced including the pixel detector. This new pixel detector requires a control system which complies with the strict requirements in terms of radiation hardness and material budget in ATLAS. The University of Wuppertal is developing a DCS (Detector...
Sergey Katunin
(B.P. Konstantinov Petersburg Nuclear Physics Institute (PNPI), 188300 St. Petersburg, Russia)
9/20/12, 5:50 PM
Poster
Precision sound velocity measurements can simultaneously determine binary gas composition and flow. We have developed an ultrasonic analyzer with custom electronics, currently in expanding use within the ATLAS experiment, with numerous potential applications.
The ATLAS silicon tracker compressor-based C3F8 evaporative cooling system will be replaced with a thermosiphon and may also circulate...
Josef Novy
(C),
Martin Bodlak
(Czech Technical University (CZ)),
Vladimir Jary
(Czech Technical University (CZ))
9/20/12, 5:51 PM
Poster
The current data acquisition system (DAQ) of the COMPASS experiment at CERN uses the DATE package installed on standard x86 compatible server machines for event building. This system does not scale well with increasing data and trigger rates. Therefore we develop a new DAQ system that would perform detector readout and event building in a custom made FPGA based hardware. The software part...
Elena Pedreschi
(Sezione di Pisa (IT))
9/20/12, 5:52 PM
Poster
The main goal of the NA62 experiment at the CERN SPS is to measure the branching ratio of the ultra-rare K+ → π+νν decay, collecting about 100 signal events in 2 years. Readout uniformity of sub-detectors, scalability, efficient online selection and loss-less readout at high rate are key issues. The TEL62 is the principal block of the Na62 DAQ and his architecture is based on a star...
Gregory Rakness
(Univ. of California Los Angeles (US))
9/20/12, 5:53 PM
Poster
In high energy physics experiments such as the Compact Muon Solenoid (CMS), electronics located near the interaction region are prone to soft (i.e., recoverable) errors as a result of radiation coming from the collisions. Depending on the type of error, the scope of their impact on data collection can range from being hardly noticeable to being completely debilitating. Here, we present...
Wojciech Bialas
(CERN)
9/20/12, 5:54 PM
Poster
We describe the observation and mitigation of anomalous, large signals, observed in the barrel part of the CMS Electromagnetic Calorimeter during proton collisions. Laboratory and beam tests, as well as simulations, have been used to understand their origin. They are ascribed to direct energy deposition by particles in the avalanche photodiodes used for light readout. A reprogramming of the...
Mr
Patrick Vogler
(Institute for Particle Physics, ETH Zurich)
9/20/12, 5:55 PM
Poster
Within the FACT project, we constructed the first full-scale Cherenkov telescope camera based on Geiger-mode avalanche photodiodes (G-APDs). Compared to photomultipliers, G-APDs are more robust, need lower operation voltage and promise higher efficiency and lower cost.
The FACT camera comprises 1440 pixels and readout channels, based on the DRS4 analog pipeline chip and features fully...
Dr
Francesco Gonnella
(LNF (IT))
9/20/12, 5:56 PM
Poster
The NA62 experiment will measure the BR(K+->π+νν) to within about 10%.
To reject the dominant background from photons, the large-angle vetoes (LAVs) must detect particles with < 1 ns time resolution and 10% energy resolution over a very large energy range.
A low threshold, large dynamic range, Time-over-threshold based solution has been developed for the LAV front end electronics. Our custom...
Steffen Lothar Muschter
(Stockholm University (SE))
9/20/12, 5:57 PM
Poster
The ATLAS Tile Calorimeter phase 2 upgrade demonstrator aims at installing a hybrid on-detector electronic system replacing 1-4 adjacent TileCal drawers in ATLAS starting end of phase 0, combining a fully functional phase 2 system with circuitry making it compatible with the present system. We are reporting a second generation prototype link and controller board connecting the drawer to...
Federico Alessio
(CERN)
9/20/12, 5:58 PM
Poster
The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire readout architecture will be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and the first hardware implementation...
David Cussans
(University of Bristol (GB))
9/20/12, 5:59 PM
Poster
We describe our apparatus built to track cosmic muons using Resistive Plate Chambers (RPC). The system consists of 12 RPCs (50 cm X 50 cm) each one coupled with 330 strips (1.5 mm pitch) and readout by means of MAROC multiplexing chips. We also present the current version of the system, where the readout is implemented using ASICs. The new system is characterized by high modularity and uses...
Craig Thorn
(Brookhaven National Laboratory)
9/20/12, 6:00 PM
Poster
The LBNE Project is developing modular multi-kiloton liquid argon time projection chambers for the Long Baseline Neutrino Experiment. A complete electronic readout system operating in LAr for 20 years is essential to this design. We are developing 180 nm commercial technology CMOS ASICs, with low-noise readout of the TPC wires, digitization, zero-suppression, buffering and output...
Nick Ryder
(University of Oxford (GB))
9/20/12, 6:01 PM
Poster
Silicon photomultipliers are robust, low power detectors for low light levels. This, along with the low bias voltages and their relatively low cost makes them a good candidate for portable scintillation detectors. A data acquisition system based around a microcontroller has been developed for such a detector with a small number of data channels. Different powering and data recording or...
Prof.
Massimo Violante
(Turin Politecnico)
9/21/12, 9:00 AM
Reconfigurable FPGAs are very appealing for mission critical applications where the capability of changing the hardware functionality on-the-fly (i.e., without expensive and time consuming maintenance operations) is a breakthrough. Space missions, as well as high energy physics experiments may benefit from the reconfiguration capability that modern FPGAs offer, but the designers have to face...
Dr
Mike Wirthlin
(Brigham Young University, Provo, Utah)
9/21/12, 9:45 AM
Oral
Field Programmable Gate Arrays (FPGAs) are an attractive alternative to application specific integrated circuits (ASICs) because of their in-field reprogrammability, low non-recurring engineering costs (NRE), and relatively short design cycle. They provide high logic density, access to the latest I/O standards, and can be designed with a variety of low-cost tools. FPGAs are increasingly used...
Johan Alme
(Bergen University College (NO))
9/21/12, 10:10 AM
Oral
The ALICE Time Projection Chamber (TPC) is the main tracking detector of ALICE. In the Readout Control Unit (RCU) an SRAM based FPGA from Xilinx controls the read out of data from the detector. Functional failures due to single event upsets are possible in the SRAM configuration memory of the FPGA. This paper presents the results of fault injection tests that have been performed to...
Jason Gilmore
(Texas A & M University (US))
9/21/12, 11:05 AM
Oral
With the forthcoming High Luminosity LHC accelerator upgrade, the CMS Endcap Muon system will require new electronics to handle the increased data rate while maintaining high data collection efficiency. Maintaining trigger efficiency for pseudorapidity above 2.1 requires deployment of higher performance electronics already in 2013. With the increased luminosity, the new electronics will be...
Mohsine Menouni
(Universite d'Aix - Marseille II (FR))
9/21/12, 11:30 AM
Oral
The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU.
Tests have shown that DICE latches where layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches.
For the future pixel readout design,...
Dr
Will Moore
(Engineering Science, University of Oxford)
Basic Parameters: Signal amplitudes and speeds, di/dt, dv/dt. R, L and C of typical structures, noise.
Basic signal integrity issues: Resistance, ground loops and differential signaling, capacitive coupling and shielding, inductive coupling and cancellation, RFI.
Impact on high-speed digital circuits: propagation speeds, transmission lines, matching and measurements, power rail decoupling,...
Dr
Will Moore
(Engineering Science, University of Oxford)
High-speed data transfer: parallel vs. serial communication, synchronous vs. asynchronous, common mode noise & differential signaling, examples such as Gigabit Ethernet and DDR memories.
Signal integrity on PCB: multilayer boards, power and ground planes, placement of components and vias, separation of analogue and digital circuits.
Signal integrity inside ICs: decoupling, low-inductance...
Ms
Fan Zhang
(Huazhong Normal University)
Poster
The current EMCal readout electronics uses bus network architecture. The readout rate is limited by the low bandwidth utilization efficiency of the data bus. A new readout electronics which uses point-to-point link and star network architecture has been developed. It is built based on the current EMCal Front-end Electronics (FEE) cards and the ALICE online systems. A specific FEE adapter card...
