Conveners
POSTERS: First Session
- Mitch Newcomer (University of Pennsylvania)
POSTERS: Second Session
- Mitch Newcomer (University of Pennsylvania)
Description
First Session
Datao Gong
(Southern Methodist Univeristy)
9/18/12, 5:00โฏPM
Poster
We present a high-speed, low power serializer ASIC, LOCs2, for the ATLAS liquid argon calorimeter upgrade. The ASIC consists of two 8 Gbps serializer channels, each of which has a 16-bit parallel data input in LVDS and a serial data output in CML logic. The ASIC is designed and fabricated in a 0.25-um commercial silicon-on-sapphire CMOS technology which is suitable for the high energy physics...
113.
An 8-channel Programmable 80/160/320 Mbit/s Radiation-Hard Phase-Aligner Circuit in 130 nm CMOS
Filip Francis Tavernier
(CERN)
9/18/12, 5:01โฏPM
Poster
The design of an 8-channel phase aligner is presented that is to be used in the GBTX chip for the LHC upgrade program. The circuit is able to align the phases of up to 8 parallel data streams to the GBTX transmitter clock so that the data can be serialized. The bit rate is programmable between 80, 160 or 320 Mbit/s. Data jitter up to ยฑ 3โขTbit/8 can be tolerated without compromising the...
Dr
FREDERIC MOREL
(IPHC-UDS-IN2P-CNRS)
9/18/12, 5:02โฏPM
Poster
A 48 ร 64 pixels prototype CMOS pixel sensor integrated with 4-bit column-level, self triggered ADCs for the ILD vertex detector outer layers was developed and fabricated in a 0.35 ยตm CMOS process with a pixel pitch of 35 ยตm. The pixel concept combines in-pixel amplification with a correlated double sampling operation. The ADCs accommodating the pixel read out in a rolling shutter mode...
Futian Liang
(University of Science and Technology of China; Southern Methodist University)
9/18/12, 5:03โฏPM
Poster
We present the design and the preliminary test results of LOCld1 and LOCld4, the VCSEL drivers fabricated in a commercial 0.25-um silicon-on-sapphire (SOS) CMOS process for the ATLAS liquid argon calorimeter upgrade. Because of the bandwidth limitation of the process, we use an active shunt peaking technique, multiple-stage amplification and a voltage higher than the nominal voltage to achieve...
Mr
Hans Kristian Soltveit
(Physikalisches Institut)
9/18/12, 5:04โฏPM
Poster
A Millimeter Wave Chip for a possible upgrade of the ATLAS Fast Tracker is under development. The 60 GHz unlicensed frequency band is of particular interest for indoor point-to-point multi gigabit data transfer due to its very large amount of spectral bandwidth (7-9 GHz). The targeted data rate for the first prototype is 3 Gbps. In this talk the key building blocks will be described, the...
Riccardo Travaglini
(Universita e INFN (IT))
9/18/12, 5:05โฏPM
Poster
The Insertable B-layer is planned for the upgrade of the ATLAS at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations...
Jan Scheirich
(Charles University (CZ))
9/18/12, 5:06โฏPM
Poster
DEPFET is an active pixel particle detector, in which a MOSFET is integrated in each pixel, providing first amplification stage of readout electronics. Excellent signal over noise performance is provided this way. The DEPFET sensor is planned to be used as an inner pixel detector in the BELLE II experiment at electron-positron SuperKEKB collider in Japan. Gated operation of the DEPFET is a...
Jim Hoff
(Fermilab)
9/18/12, 5:07โฏPM
Poster
Future LHC experiments demand greater speed and orders of magnitude more patterns from associative memory-based track finders. The scaling of current technology in 2D is unlikely to satisfy the scientific needs. New technology will be needed. 3D Vertical Integration not only provides more active silicon per unit area creating higher pattern density, but also permits geometrical...
Simone Esch
(IKP, Forschungszentrum Jรผlich)
9/18/12, 5:08โฏPM
Poster
The Micro Vertex Detector (MVD) is the innermost tracking detector of the PANDA experiment at the upcoming FAIR facility in Darmstadt. The detector consists of several layers of silicon pixel and strip sensors to obtain precise tracking of charged particles.
For the development of a front-end ASIC a flexible and powerful readout system was developed to interface different ASIC prototypes.
We...
Marius Wensing
(Bergische Universitaet Wuppertal (DE))
9/18/12, 5:09โฏPM
Poster
For the coming upgrade of the ATLAS pixel detector at CERN a redesign of the current data readout is necessary. To communicate with the additional 448 front-end chips assembled in the Insertable B-Layer (IBL) new FPGA readout cards consisting of a Back of Crate card (BOC) and a Read Out Driver (ROD) have been developed. This paper will describe the firmware and hardware development of the new...
Dr
Tiankuan Liu
(Southern Methodist University)
9/18/12, 5:10โฏPM
Poster
We propose a line code for the optical data links of the ATLAS liquid argon calorimeter upgrade. The line encoder inserts a frame trailer at the end of each data frame before the data are scrambled and the line decoder recovers the beginning and end of each frame, descrambles the data frame, and removes the frame trailer. The line code has low latency, low overhead, fast resynchronization...
Dr
Paschalis Vichoudis
(CERN)
9/18/12, 5:18โฏPM
Poster
The Gigabit Link Interface Board (GLIB) project is an FPGA-based platform for users of high-speed optical links in high energy physics experiments. The major hardware component is the GLIB Advanced Mezzanine Card (AMC). Additionally to the GLIB AMC, auxiliary add-on boards are under development in order to enhance the GLIB AMC I/O bandwidth and compatibility with legacy and future triggering...
Lauri Juhani Olantera
(CERN)
9/18/12, 5:19โฏPM
Poster
The Versatile Transceiver is a part of the Versatile Link project, which is developing optical link architectures and components for future HL-LHC experiments. While having considerable size and weight constraints Versatile Transceivers must work in severe environmental conditions. One such environmental parameter is the temperature: the operating temperature range is specified to be from -30...
Mr
Mikhail Matveev
(Rice University)
9/18/12, 5:20โฏPM
Poster
We present the results of initial tests of prototype optical links of an upgraded trigger for the Cathode Strip Chamber sub-detector at the CMS experiment at CERN. After presenting an overview of the existing system and upgrade requirements, we describe the hardware and firmware developed to drive the new links.
Results of initial tests with the prototype Track Finder board and...
Deepak Gajanana
(NIKHEF)
9/18/12, 5:21โฏPM
Poster
Particle detectors in High Energy Physics experiments, contain various types circuits and demand data rates of multiple Gbps per chip and several Tbps for the whole detector. Optical transmission by external modulation of a continuous wave laser is a possible solution to tackle the problem of high data rates.In this paper, we investigate the radiation hardness performance of InP-based...
Alvaro Navarro Tobar
(Centro de Investigaciones Energ. Medioambientales y Tecn. - (ES)
9/18/12, 5:22โฏPM
Poster
CMS DT electronics upgrade involves laying down 3500 optical links from the CMS cavern to the counting room, whose lengths must be matched to minimize skew, so that the present upstream electronics can be reused at an initial stage. In order to assess the cablesโ compliance, a high resolution and cost-effective system has been developed to measure the length uniformity of these fibres....
Paolo De Remigis
(INFN sez. di Torino)
9/18/12, 5:23โฏPM
Poster
The upgrade of the Drift Tube system of the CMS experiment foresees the relocation of the Sector Collector from the cavern to the counting room. It is thus required to convert the signals from electrical to optical, for a total number of 3500 channels running up to 480 Mb/s. A Copper to Optical Fiber (CuOF) board is currently under design. The board is divided into a mother board, which hosts...
annie xiang
(Southern Methodist University)
9/18/12, 5:24โฏPM
Poster
The 120Gbps optical transmitter is a 12-channel, 10Gbps per channel, parallel pluggable module to operate on the detector front-end for the readout and control of High-Luminosity LHC (HL-LHC) experiments. We present the design concepts based on multiple TOSAs, precision array coupling and drop-in opto engines. We describe the prototype development and the experimental set-up for parametric...
Giovanni Mazza
(INFN sez. di Torino)
9/18/12, 5:31โฏPM
Poster
The readout architecture for the silicon pixel sensors of the PANDA MVD is presented.The pixel detector has to provide timing, position and energy information on a event-driven base, since no trigger signal is foreseen.
The readout system is based on a custom ASIC, named ToPiX, directly connected to the GBT optical transceiver. A reduced size prototype with most of the main functionality has...
Mr
Alan Prosser
(Fermilab)
9/18/12, 5:32โฏPM
Poster
We have designed an advanced test-beam facility including a pixel tracking telescope. In the data path between the telescope and a PC, a commercial MicroTCA crate houses an Advanced Mezzanine Card (AMC) which receives, buffers, and processes the data from the tracking telescope, transmitting complete assembled events to the PC in real-time. This approach makes possible rapid assessment of the...
Steven Welch
(Oklahoma State University (US))
9/18/12, 5:33โฏPM
Poster
The ATLAS Pixel new Service Quarter Panel (nSQP) project aims to deliver replacements for all on-detector services of the ATLAS Pixel Detector. The nSQPs will have LVDS transceivers at the place of the present electro-optical converters. The transceivers, realized in 130 nm technology, communicate with the existing ATLAS Pixel MCC chips, and over a 6.6m long electrical transmission line with...
Ms
Sandra Saornil Gamarra
(Universitaet Zuerich (CH) on behalf of LHCb Silicon Tracker group)
9/18/12, 5:34โฏPM
Poster
The LHCb Silicon Tracker is part of the main tracking system of the LHCb detector at the LHC. It measures very precisely the particle trajectories coming from the interaction point in the region of high occupancies around the beam axis.
After presenting our production and comissioning issues in TWEPP 2008, we report on our running experience. Focusing on electronic and hardware issues as...
Sam Cook
(University College London)
9/18/12, 5:35โฏPM
Poster
The clock and control (CC) system for the EuXFEL megapixel detectors was presented in TWEPP 2011. It consists of a multipurpose MTCA.4 AMC card with an FPGA and a custom designed Rear Transition Module (RTM). This paper presents the experiences with the system since its first prototype and the development of the final hardware. Experiences with the hardware included the tests performed to...
Mr
Robert Schnell
(HISKP, University Bonn; II. Phys. Inst., University Giessen)
9/18/12, 5:36โฏPM
Poster
The PANDA experiment at the future FAIR facility will study annihilation reactions of antiprotons. The Micro-Vertex-Detector as part of the tracking system will permit precise tracking and detection of secondary vertices. It is made of silicon pixel detectors and double-sided silicon strip detectors.
Aspects of the development for the strip detector will be presented: Evaluation of prototype...
Janos Ero
(Austrian Academy of Sciences (AT))
9/18/12, 5:43โฏPM
Poster
The upgrade of the Drift Tube Track Finder (DTTF) electronics will be designed using VHDL synthesis. The construction of the HDL structure merges improved blocks of the Track Finding algorithms and the results of the CMS wide detector control, monitoring and DAQ output common development. This merged design is subject of extended simulations both on behavioral level and concerning the timing...
Volker Wenzel
(Johannes-Gutenberg-Universitaet Mainz (DE))
9/18/12, 5:44โฏPM
Poster
By 2014 the LHC will collide proton bunches at 14 TeV with an increased instantaneous luminosity up to 3ร10^34cmโ2sโ1. A reduction on the trigger rate can be achieved by applying topological cuts adopting a new FPGA based module in the L1 trigger: the Topological Processor (TP). This presentation focuses on the design of the first TP prototype and on the test results on algorithm implemented...
Ben Cooper
(University College London)
9/18/12, 5:45โฏPM
Poster
The increased collision rate and pile-up produced at the HLLHC requires a substantial upgrade of the ATLAS level-1 trigger in order to maintain a broad physics reach. We show that tracking information can be used to control trigger rates, and describe a proposal for how this information can be extracted within a two-stage level-1 trigger design that has become the baseline for the HLLHC...
Victor Andrei
(Ruprecht-Karls-Universitaet Heidelberg (DE))
9/18/12, 5:46โฏPM
Poster
The ATLAS Level-1 Calorimeter Trigger is a pipelined system to identify high-pT objects and to build energy sums within a fixed latency of ~2 us. It consists of a PreProcessor, which conditions and digitises analogue calorimeter signals, and two object-finding processors. The PreProcessor's tasks are implemented on a Multi-Chip Module, holding ADCs, time-adjustment and digital processing...
Mr
Raul Esteve
(Universitat Politรจcnica de Valรจncia)
9/18/12, 5:47โฏPM
Poster
NEXT-DEMO is a large-scale prototype of NEXT, an experiment to search for neutrinoless double beta decays using a radiopure high-pressure gaseous xenon TPC with electroluminescence readout. Based on a PMT plane for energy measurements and a SiPM tracking plane for topological event filtering, front-end electronics, trigger and data-acquisition systems (DAQ) have been built. The DAQ is a...
Mr
Jose Carlos Da SIlva
(LIP LISBON)
9/18/12, 5:48โฏPM
Poster
The calorimeter trigger synchronization of the Compact Muon Solenoid experiment at the large hadron collider (LHC) uses a synchronization method implemented in the synchronization and link board (SLB). The board allows the synchronization of electromagnetic and hadronic trigger primitives at the LHC frequency (40.08 MHz) and its transmission to the Regional Calorimeter Trigger. The new...
Dr
Andrew William Rose
(Imperial College Sci., Tech. & Med. (GB))
9/18/12, 5:49โฏPM
Poster
Test results are presented for two AMC cards, the "CTP6" and "MP7", along with results from a custom Vadatech VT893 backplane. The two cards take different approaches to connectivity: one with fully-populated backplane connectivity and a 396Gbps asymmetric, optical interface, the other favouring, instead, a 1.4Tbps, symmetric, all-optical interface. The challenges of designing these cards...
Deepak Gajanana
(NIKHEF)
9/20/12, 5:00โฏPM
Poster
In the KM3NeT project, the electronics required to control the PMTs and collect the signals is integrated in two ASICs: 1. Front-end mixed signal ASIC (PROMiS) and 2. Analog ASIC (CoCo) to control the feedback of the high voltage (HV) circuit. We discuss the two integrated circuits and their test results. The read out ASIC amplifies converts input charge to pulse width and delivers the...
Alessandro Gabrielli
(Universita e INFN (IT))
9/20/12, 5:01โฏPM
Poster
We describe the design of a floating gate-based MOS sensor embedded in a read-out CMOS sensing element used as a radiation sensor. A maximum sensitivity of 1mV/rad is estimated up to 10krad. The paper shows the design of a microelectronic circuit that includes a sensor, an oscillator and modulator, which is now under fabrication. Given the small estimated area of the complete chip prototype,...
Selma Conforti Di Lorenzo
(OMEGA/LAL/IN2P3/CNRS)
9/20/12, 5:02โฏPM
Poster
The SPIROC chip is a dedicated very front-end electronics to read out a prototype of the Analog Hadronic Calorimeter (AHCAL) equipped with Silicon Photomultiplier (SiPM) for ILC (International Linear Collider).
A first prototype of SPIROC has been fabricated in 2007 and a second version in 2010. Many testbench and testbeam measurements have been performed showing a good overall behaviour....
Mr
Shiming Deng
(IPNL)
9/20/12, 5:03โฏPM
Poster
For developing a scintillating-fiber beam monitor, we have designed a front-end 16-Channels readout chip to be associated with PMTs in a 0.35 ยตm BiCMOS process. Each channel consists of one input current conveyor driving separately a current comparator for signal event detection and a charge-sensitive amplifier for signal charge measurement. The ASIC version 2 has brought significant...
Claudio Gotti
(University of Firenze and INFN Milano Bicocca)
9/20/12, 5:05โฏPM
Poster
An ASIC named CLARO-CMOS was designed for fast photon counting with MaPMTs, MCPs and SiPMs. The ASIC was realized in a .35 um CMOS technology, and has 4 channels, each with a fast amplifier and a discriminator. The main features of the design are the high speed of operation, aiming to completely eliminate the dead time at a 40 MHz event rate, and low power dissipation, around 1 mW/ch and...
Albert Comerma Montells
(Universidad de Barcelona)
9/20/12, 5:06โฏPM
Poster
A Front End ASIC for the readout of Silicon Photo-Multipliers is presented with the following features:
wide dynamic range, high speed, multi channel, low input impedance current preamplifier, low power (7mW per channel), DC coupled input with common mode voltage control and separated timing and charge signal output.
A detailed description of the SiPM modeling and parameter extraction is...
Edgar Lemos Cid
(Universidade de Santiago de Compostela (ES))
9/20/12, 5:13โฏPM
Poster
The goal of this project is to examine the feasibility of data transmission up to ~5Gbit/s on a short (~60cm) low mass flex cable. These cables will be used for the readout of the upgraded vertex detector (VELO) of the LHCb experiment in high radiation and vacuum environment. We present a study of different transmission line geometries, the effect of using fine pitch (400ฮผm) connectors, the...
Georges Blanchot
(CERN)
9/20/12, 5:14โฏPM
Poster
The upgrade of the CMS tracker at the HL-LHC requires the design of new front-end modules to cope with the increased luminosity and to implement L1 trigger functionnality. The new modules under development are based on high density hybrid circuits with new flip-chip front-end ASIC, and are wire bonded to strip sensors and connected to a service board for the data transmission. The suitability...
Alessandro Mapelli
(CERN)
9/20/12, 5:15โฏPM
Poster
Microchannel cooling has been selected for the thermal management of the NA62 GTK detector. The baseline design is based on a 130 micron thick silicon microstructured plate spanning over the whole sensor surface. An alternative design, based on a "frame-like" geometry, is also under study. Experimental measurements detailing the performance of both configurations will be presented and...
Dr
Paschalis Vichoudis
(CERN)
9/20/12, 5:22โฏPM
Poster
In March 2012 the high voltage system of the silicon-sensor-based CMS Preshower detector underwent a significant upgrade. In addition to a doubling of the number of power supplies, a new active distribution board was developed and installed. This new board provides much improved flexibility in the powering, necessary to cope with the expected evolution of the 4288 silicon sensors with...
Peter Phillips
(STFC - Science & Technology Facilities Council (GB))
9/20/12, 5:23โฏPM
Poster
The engineering challenges related to the supply of electrical power to future large scale detector systems are well documented. The ATLAS Upgrade Strip Tracker Community has previously presented results from two demonstrator stavelets, one serially powered and one built with DC-DC convertors. Both approaches have the potential to increase the efficiency of the powering system.
At the time...
Alessandro Bartoloni
(Universita e INFN, Roma I (IT))
9/20/12, 5:24โฏPM
Poster
The CMS electro-magnetic calorimeter comprises 75848 scintillating lead tungstate crystals. 61200 crystals are contained in the ECAL Barrel section and these are readout by avalanche photodiodes (APD) with internal gain. The APD gain strongly depends on the bias voltage that, for a gain G=50, is around 400 V. In order to match the requirements for gain stability, the power supply voltage must...
Michal Bochenek
(University of Pennsylvania (US))
9/20/12, 5:25โฏPM
Poster
The power distribution systems in the ATLAS Inner Tracker Upgrade require linear voltage regulators on the front-end chips to be the last stages of the powering chain. In the paper we present two designs: a classical voltage regulator based on an NMOS transistor as the pass element and an LDO voltage regulator employing a PMOS device. Both prototype regulators have been implemented in the...
Maria Cristina Esteban Lallana
(Aragon Institute of Technology (ES))
9/20/12, 5:26โฏPM
Poster
The next generation of CMS tracker system will have all DC-DC converters located inside the tracker volume.They will be connected together in each rod via common power network, which propagates this noise along the rod.This paper presents several conducted and radiated test results on a prototype of the Pt power network.Test results will show the implication of the DC-DC converter position and...
Cristian Alejandro Fuentes Rojas
(CERN)
9/20/12, 5:27โฏPM
Poster
The precision requirements of the vertex detector at CLIC impose strong limitations on the mass of such a detector (<0.2 X0 per layer). To achieve such a low mass, ultra-thin hybrid pixel detectors are foreseen, while the mass for cooling and services will be reduced by implementing a power-pulsing scheme that uses the low duty cycle of the accelerator. The principal aim is to achieve...
Jennifer Jentzsch
(Technische Universitaet Dortmund (DE))
9/20/12, 5:34โฏPM
Poster
For the first ATLAS pixel upgrade scheduled in 2013 a new front-end chip generation (FE-I4) has been developed. The second version (FE-I4B) hosting two different solid-state sensor technologies (planar silicon and 3D silicon) has been produced to be built into a new pixel layer (the Insertable B-Layer, IBL). Prototypes of these assembled modules have been tested in laboratory and testbeam...
Pablo Moreno
(Universidad de Valencia)
9/20/12, 5:35โฏPM
Poster
This paper describes a new portable test bench for the TileCal sub-detector of the ATLAS experiment at CERN. The system is used for the certification and quality checks of the front-end electronics drawers. It is designed to be an easily upgradable version of the current 10-year-old system, able to evaluate the new technologies planned for the upgrade as well as provide new functionality to...
Vladimir Zivkovic
(NIKHEF Institute)
9/20/12, 5:36โฏPM
Poster
The article addresses production test development effort of the ATLAS FE-I4 integrated circuit. This particular production test targets manufacturing faults in the ICs and has been taken as a supplementary approach, besides standard functional test, to decrease further the risk of potential application failures. The Design-for-Test structures inside the digital part of the chip together with...
58.
New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC
Lukas Pรผllen
(Uni-Wuppertal)
9/20/12, 5:43โฏPM
Poster
In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled. In this upgrade, the inner detector of the ATLAS experiment will be replaced including the pixel detector. This new pixel detector requires a control system which complies with the strict requirements in terms of radiation hardness and material budget in ATLAS. The University of Wuppertal is developing a DCS (Detector...
Sergey Katunin
(B.P. Konstantinov Petersburg Nuclear Physics Institute (PNPI), 188300 St. Petersburg, Russia)
9/20/12, 5:50โฏPM
Poster
Precision sound velocity measurements can simultaneously determine binary gas composition and flow. We have developed an ultrasonic analyzer with custom electronics, currently in expanding use within the ATLAS experiment, with numerous potential applications.
The ATLAS silicon tracker compressor-based C3F8 evaporative cooling system will be replaced with a thermosiphon and may also circulate...
Josef Novy
(C),
Martin Bodlak
(Czech Technical University (CZ)),
Vladimir Jary
(Czech Technical University (CZ))
9/20/12, 5:51โฏPM
Poster
The current data acquisition system (DAQ) of the COMPASS experiment at CERN uses the DATE package installed on standard x86 compatible server machines for event building. This system does not scale well with increasing data and trigger rates. Therefore we develop a new DAQ system that would perform detector readout and event building in a custom made FPGA based hardware. The software part...
Elena Pedreschi
(Sezione di Pisa (IT))
9/20/12, 5:52โฏPM
Poster
The main goal of the NA62 experiment at the CERN SPS is to measure the branching ratio of the ultra-rare K+ โ ฯ+ฮฝฮฝ decay, collecting about 100 signal events in 2 years. Readout uniformity of sub-detectors, scalability, efficient online selection and loss-less readout at high rate are key issues. The TEL62 is the principal block of the Na62 DAQ and his architecture is based on a star...
Gregory Rakness
(Univ. of California Los Angeles (US))
9/20/12, 5:53โฏPM
Poster
In high energy physics experiments such as the Compact Muon Solenoid (CMS), electronics located near the interaction region are prone to soft (i.e., recoverable) errors as a result of radiation coming from the collisions. Depending on the type of error, the scope of their impact on data collection can range from being hardly noticeable to being completely debilitating. Here, we present...
Wojciech Bialas
(CERN)
9/20/12, 5:54โฏPM
Poster
We describe the observation and mitigation of anomalous, large signals, observed in the barrel part of the CMS Electromagnetic Calorimeter during proton collisions. Laboratory and beam tests, as well as simulations, have been used to understand their origin. They are ascribed to direct energy deposition by particles in the avalanche photodiodes used for light readout. A reprogramming of the...
Mr
Patrick Vogler
(Institute for Particle Physics, ETH Zurich)
9/20/12, 5:55โฏPM
Poster
Within the FACT project, we constructed the first full-scale Cherenkov telescope camera based on Geiger-mode avalanche photodiodes (G-APDs). Compared to photomultipliers, G-APDs are more robust, need lower operation voltage and promise higher efficiency and lower cost.
The FACT camera comprises 1440 pixels and readout channels, based on the DRS4 analog pipeline chip and features fully...
Dr
Francesco Gonnella
(LNF (IT))
9/20/12, 5:56โฏPM
Poster
The NA62 experiment will measure the BR(K+->ฯ+ฮฝฮฝ) to within about 10%.
To reject the dominant background from photons, the large-angle vetoes (LAVs) must detect particles with < 1 ns time resolution and 10% energy resolution over a very large energy range.
A low threshold, large dynamic range, Time-over-threshold based solution has been developed for the LAV front end electronics. Our custom...
Steffen Lothar Muschter
(Stockholm University (SE))
9/20/12, 5:57โฏPM
Poster
The ATLAS Tile Calorimeter phase 2 upgrade demonstrator aims at installing a hybrid on-detector electronic system replacing 1-4 adjacent TileCal drawers in ATLAS starting end of phase 0, combining a fully functional phase 2 system with circuitry making it compatible with the present system. We are reporting a second generation prototype link and controller board connecting the drawer to...
Federico Alessio
(CERN)
9/20/12, 5:58โฏPM
Poster
The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire readout architecture will be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and the first hardware implementation...
David Cussans
(University of Bristol (GB))
9/20/12, 5:59โฏPM
Poster
We describe our apparatus built to track cosmic muons using Resistive Plate Chambers (RPC). The system consists of 12 RPCs (50 cm X 50 cm) each one coupled with 330 strips (1.5 mm pitch) and readout by means of MAROC multiplexing chips. We also present the current version of the system, where the readout is implemented using ASICs. The new system is characterized by high modularity and uses...
Craig Thorn
(Brookhaven National Laboratory)
9/20/12, 6:00โฏPM
Poster
The LBNE Project is developing modular multi-kiloton liquid argon time projection chambers for the Long Baseline Neutrino Experiment. A complete electronic readout system operating in LAr for 20 years is essential to this design. We are developing 180 nm commercial technology CMOS ASICs, with low-noise readout of the TPC wires, digitization, zero-suppression, buffering and output...
Nick Ryder
(University of Oxford (GB))
9/20/12, 6:01โฏPM
Poster
Silicon photomultipliers are robust, low power detectors for low light levels. This, along with the low bias voltages and their relatively low cost makes them a good candidate for portable scintillation detectors. A data acquisition system based around a microcontroller has been developed for such a detector with a small number of data channels. Different powering and data recording or...
