A line code is commonly used in a digital data transmission system for the purposes of clock recovery, DC balance and word boundary recovery. In the optical data link R&D for the ATLAS liquid argon calorimeter upgrades, we envisage the following requirements that call for a custom line code. First, the serial output data from 16 analog-digital-converters (ADCs) are transmitted in a single optical fiber. The receiver must be able to detect which ADC the data come from (i.e., the word boundary) and where a digitization starts and ends (i.e., the frame boundary). However, the commonly used line codes have no framing function. It is favorable to combine the low-level line code and the high-level framing to reduce the overhead. Second, an optical data link operating in a harsh radiation environment may be disturbed by single-event effects. For example, in the irradiation test of a serializer ASIC we have observed a one-bit data shift following a burst of errors. It is highly desirable that a line code have a fast resynchronization capability to minimize data loss. Third, in the ATLAS liquid argon calorimeter (LAr) upgrade, the data transmitted through an optical link is used to acquire a trigger signal. Due to the size limit of the analog buffers, the latency of the encoder and the decoder should be kept as low as possible. Fourth, a bunch crossing identification (BCID) should be embedded in the data for event identification and the alignment of optical link channels.
A new line code has been proposed for the optical data links of the ATLAS liquid argon calorimeter upgrade. The encoder inserts a frame trailer at the end of each frame, the data packet of a digitization sample of 16 ADC channels. Each frame trailer consists of a 12-bit pseudo-random binary sequence (PRBS) and a 4-bit cyclic redundancy error detection code. The decoder uses the PRBS code to recover the word boundary and frame boundary. The PRBS code is also an embedded BCID. The data which exclude the frame trailer are scrambled before they are transmitted. The simulation with the ATLAS data format indicates that the scrambled data meet the maximum run length constraints of commercial clock-data recover circuits.
The line code has low latency, low overhead, fast resynchronization capability and flexible frame size. The encoder and the decoder have been validated in an FPGA and the performance has been evaluated. The latency of the encoder is less than 4.2 ns and that of the decoder is less than 8.4 ns. The overhead of this code is 8.3% for 12-bit ADCs sampling at 40 MS/s. The decoder is capable to resynchronize within one frame, even faster than 8B/10B encoding.
The encoder will be integrated into an ASIC together with a serializer in the future. The application background, code definition, validation, and performances of the line code are presented.