TWEPP 2012 Topical Workshop on Electronics for Particle Physics

17 Sept 2012, 10:00 → 21 Sept 2012, 18:00 Europe/Zurich

Oxford University, UK

Philippe Farthouat (CERN)

The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.

LHC experiments (and their operational experience) will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.

The purpose of the workshop is :

- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities

- to review the status of electronics for the LHC experiments

- to identify and encourage common efforts for the development of electronics

- to promote information exchange and collaboration in the relevant engineering and physics communities.


 

Monday, 17 September

14:00 → 15:00 Welcome

Convener: Dr Todd Brian Huffman (University of Oxford (GB))

14:00 TWEPP-12 Opening

Speaker: Philippe Farthouat (CERN)

Slides TWEPP12-Opening.pdf TWEPP12-Opening.pptx

14:15 Welcome from the Local Organising Committee

Speaker: Dr Todd Brian Huffman (University of Oxford (GB))

Slides WelcometoOxfordTWEPP2012.pdf WelcometoOxfordTWEPP2012.pptx

14:30 Welcome from the Chair of Physics

Speaker: Dr John Wheater (University of Oxford)

15:00 → 16:00 Opening 1

Convener: Dr Todd Brian Huffman (University of Oxford (GB))

15:00 Lady Margaret Hall and collegiate Oxford

Lady Margaret Hall is one of thirty colleges in the University of Oxford that educate both undergraduate and graduate students. A further seven colleges are for graduates only, and one – All Souls – has only fellows. Each college has its own history and style. LMH was founded in 1878 to enable women to study at Oxford for the first time. In 1978 it became co-educational. It has always retained the spirit of openness and equality, and the commitment to scholarship, that inspired its foundation.

Speaker: Dr Frances Lannon (Oxford University)

15:20 Technical support and activities in Oxford

Oxford’s Department of Physics champions the notion that Physics Research needs strong technical support. To this end it has around 40 staff providing Mechanical, Photo Fabrication and Electronics Engineering and related manufacturing support using a wide range of modern tools. In recent years these services have been designated as cost recovered services allowing them to provide support for other local University Departments as well as other organisations. Due to their unique capability to produce components that cannot be easily sourced elsewhere they have been successful in bringing in work from academic institutes from around the world. This talk will give you a flavour of what Oxford can do for you.

Speaker: Johan Fopma (University of Oxford)

Slides TWEPP2012_Fopma_17-9-12.pdf TWEPP2012_Fopma_17-9-12.pptx

16:00 → 16:30 Break

16:30 → 18:55 Opening 2

Convener: Philippe Farthouat (CERN)

16:30 Advanced Electronics Developments at the STFC National Laboratory

The UK Science and Technology Facilities Council (STFC) provides electronics and instrumentation solutions to large scale scientific facilities in the UK and world-wide. The Technology Department of the STFC plays a leading role in developing, deploying and supporting the requirements of those facilities for advanced electronics and detectors. The talk will look at those facilities requirements and go on to describe past achievements, our current development activity and outline our long term strategy for the future. This includes the adoption of new fine feature sized electronics, advanced interconnect solutions and novel sensor materials.

Speaker: Mr Marcus Julian French (STFC - Science & Technology Facilities Council (GB))

Slides

• Caffeine2.avi
• MJF_TWEPP_2012_final.pdf
• MJF_TWEPP_2012_final.pptx
• shutter_100hz.avi
• shutter_1khz.avi

17:15 High speed cameras for X-rays: AGIPD and others

For the scattering experiments of X-rays at FELS’s new instruments, cameras are currently being developed to record two dimensional images with increased picture rate and the feature to store scatterings of individual X-ray bunches on the targets. Combined with the very intense bunches of FEL’s this will allow to extract the structure of the target from scattering of individual bunches. The talk will be based on AGIPD - a multi-national consortium of DESY, PSI, University of Hamburg and University of Bonn. This group develops Si-sensors, ASIC’s, PCB’s and FGPA’s for a 1Mega-pixel camera with 200µm sized pixels, which will be able to record individual pictures for the bunch interval of the Eu-XFEL, 222ns. The accelerator will deliver bunches in a trained structure of 10 trains/second with each 2700 bunches. Out of them AGIPD will store 324 pictures/train and by that 3240 pictures/second. An ASIC behind the sensor will store the signals into capacitors for each pixel and bunch. Since the ASIC area for each pixel is its own size, the number of storage cells is limited. Random access will allow keeping the best scatterings for later processing. After each train the kept signals will be digitized with 33MS/s by 1024 ADC's mounted onto PCB's generating a total data stream of 0.5Tbit/s. 16 FPGA's within the detector head, each for a detector module representing a geometrical region, will do first processing and sorting. Using the full time between trains each FPGA sends its data formatted to 10GbE/UPD out of the detector-head. An ATCA based FPGA system collects them and sort them to full geometrical pictures and trains. For Eu-XFEL two other consortia develop similar cameras, LPD with larger pixels and more area for electronics and DSSC integrated the ADC's already into each pixel. AGIPD’s digital electronics with its high data throughput is also requested to be integrated into cameras used at synchrotrons. DESY contributes to the developments of PERCIVAL using MAPs techniques and to LAMBDA aiming for a combination of the MEDIPIX chips with high-Z sensors.

Speaker: Peter Goettlicher (Deutsches Elektronen-Synchrotron (DE))

Paper http://iopscience.iop.org/1748-0221/8/01/C01042

Slides TWEPP2012_AGIPD.pdf TWEPP2012_AGIPD.pptx

18:00 A Much Better Explained (hopefully) Version of the Discovery by ATLAS and CMS of a New Boson. (But we all think it is probably the Higgs Boson).

On July 4th of this year we all know what was dominating the Headlines. "Higgs boson-like discovery claimed at LHC" enthused the BBC. The New York Times was far more excited with the headline: "Physicists Find Elusive Particle Seen as Key to Universe". Many of us watched Fabiola Gianotti and Joe Incandela's talks on the discovery from ATLAS and CMS respectively and in the end saw many plots and tables, mostly about backgrounds and statistical analyses, that lead up to one or two final plots in the end setting confidence levels. In this talk I hope to take these discoveries a bit more slowly. The talk will have two main sections, the first of which will be the background to the discovery. There will be an explanation as to why the Higgs boson was invented in the first place, then given that it was, why we needed to build a machine with a radiation profile that almost no electronic equipment or sensors could survive. I will then explain how the Higgs boson decays and why only certain decay channels ended up being the ones presented in July. The second section will focus on the results obtained. I will look at the "golden channels" and explain a bit about what kind of detector is needed to find the Higgs in these channels. However, the game at this stage is all about the backgrounds and so some discussion on the largest background will be needed. The final part of the talk ends with the final plots from ATLAS and CMS from the discovery in July so that one can see how it all happened.

Speaker: Dr Todd Brian Huffman (University of Oxford (GB))

Slides TWEPP2012HiggsForEngineers.pdf TWEPP2012HiggsForEngineers.pptx

19:00 → 21:00 Welcome Reception

Tuesday, 18 September

09:00 → 09:45 P1: The World Wide Web of Glass: The Past, Present and Future of Fibre Optics

Convener: Francois Vasey (CERN)

09:00 The World Wide Web of Glass: The Past, Present and Future of Fibre Optics

Using sun and reflectors, communicating with light goes back thousands of years. But with the advent of lasers and optical fibres in the later half of the past century a revolution occurred in the telecommunications industry. A single fibre made of a flexible strand of ultra-pure silica, with a width not much greater than that of a human hair, has the capacity to transmit more than 250 million simultaneous telephone conversations, or to provide 5 million broadband internet connections. Moreover it can do this over transoceanic distances. This explosion in data transfer capacity, speed and system reach has changed the world through the internet and in order to satisfy societies ever increasing communications needs a cloak of optical fibres now covers the globe. This development of today’s fibre networks has only been possible due to a number of key scientific breakthroughs, as well as huge and sustained investment in optical fibre telecommunications technology over the years. Major advances have been required in manufacturing processes, as well as in both component and system concepts. For example, the invention of the optical fibre amplifier at Southampton University in the mid-1980s eliminated signal attenuation as a fundamental limit to the distance and speed that data can be sent through optical fibre cables. Prior to this, signals had to be converted from the optical to the electronic domain every few tens of kilometres and this imposed a huge bottleneck to system capacity. Until recently, it had been widely assumed that the transmission bandwidth available from optical fibres as developed in the mid-70’s was effectively infinite relative to our needs. However, due to increased internet uptake and the emergence of new and ever more bandwidth hungry applications, there is a growing realization that this is no longer the case and that there is a significant risk of a capacity crunch in the next 10-20 years without further radical innovation in the underpinning fibre technology. In this talk I will review the historic development of optical fibre technology and describe the current state-of-the-art in terms of transmission performance. I will then review possible ways forward to avoid the looming bandwidth-crunch ahead. Time permitting I will also describe some of the other emerging applications of fibre technology which range from demonstrating nuclear fusion, use in cutting and welding steel right through to discovering new oil reserves.

Speaker: Prof. David Richardson (University of Southampton)

Slides Oxford_final.pdf Oxford_final.pptx

09:50 → 10:40 A1a: ASICS

Convener: Mr Marcus Julian French (STFC - Science & Technology Facilities Council (GB))

09:50 Characterization of FE-I4B pixel readout chip production run for ATLAS Insertable B-Layer upgrade.

A production run of FE-I4 pixel readout chips (denominated FE-I4B) was submitted September 2011 and first wafers were received in December. These chips are being used to build the Insertable B-Layer upgrade for ATLAS, to be installed during the 2013-14 shutdown. Results will be presented for detailed probing characterization of these wafers, as well as measurements of chips on boards before and after irradiation. Based on these test results, the FE-I4B has been accepted for IBL production and the power conditioning configuration, using on-chip voltage regulators, has been finalized.

Speaker: Malte Backhaus (Universitaet Bonn (DE))

Paper http://iopscience.iop.org/1748-0221/8/03/C03013

Slides Characterization_of_FE-I4B_pixel_readout_chip_production_run.pdf

10:15 Results of 65nm pixel readout chip demonstrator array

we have explored the use of the 65 nm CMOS technology node for pixel readout. A demonstrator 500-pixel matrix containing analog front ends only (no complex functionality), was designed and fabricated in Summer 2011, and irradiated with protons in Dec. 2011 and May 2012. We present the design and measurement results for this prototype.

Speaker: Mohsine Menouni (Centre National de la Recherche Scientifique (FR))

Paper http://iopscience.iop.org/1748-0221/8/01/C01055

Slides Chip65nm_TWEPP2012_V2.pdf Chip65nm_TWEPP2012_V2.pptx

09:50 → 10:40 B1a: Optoelectronics and Links

Convener: Francois Vasey (CERN)

09:50 A PCI Express Optical Link Based on Low-Cost Transceivers Qualified for Radiation Tolerance

With this work we want to demonstrate that an optical physical medium is compatible with the second generation of PCI Express. The benefit introduced by the optical decoupling of a PCI Express endpoint is twofold: it allows for a geographical detachment of the device and it remains compliant with the usual PCI accesses to the legacy I/O and memory spaces. We propose two boards, that can bridge the PCI Express protocol over optical fiber, already working in the Drift Tube system of the CMS experiment. The positive outcome of a radiation test of the transceiver link is also reported.

Speaker: Andrea Triossi (Universita e INFN (IT))

Paper http://iopscience.iop.org/1748-0221/8/02/C02011

Slides LINCO.pptx

10:15 Modulator Based High Bandwidth Optical Readout for HEP detectors

Optical links will be an integral part of future HEP experiments at various scales from coupled sensors to off-detector communication. We are investigating light modulators as an alternative to VCSELs. Light modulators are small, use less power, have high bandwidth, are reliable, have low bit error rates and are very rad-hard. We present the quality of the links at 10GB/s and the results of radiation hardness measurements for the modulators built based on LiNbO3, InP, and Si. Also we present results on free space links, steered by MEMS mirrors and optical feedback paths for the control loop.

Speaker: David Underwood (Argonne National Laboratory (US))

Paper http://iopscience.iop.org/1748-0221/8/02/C02023

Slides TWEPP12_Underwood_V5.pdf TWEPP12_Underwood_V5.ppt

10:40 → 11:10 Break

11:10 → 12:25 A1b: ASICS

Convener: Mr Marcus Julian French (STFC - Science & Technology Facilities Council (GB))

11:10 A monolithic pixel sensor (TRAPPISTe-2) for particle physics instrumentation in OKI 0.2μm SOI technology

A monolithic Active Pixel sensor for charged particle tracking has been developed. This sensor is within the frame of a R&D project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology), with the aim of studying the feasibility of developing a Monolithic Active Pixel Sensor (MAPS)with SOI technology. TRAPPISTe-2 is the second prototype in this series and was fabricated with OKI 0.20µm fully depleted (FD-SOI) CMOS process. This Monolithic pixel sensor has been designed, fabricated and is being tested. The first results that will be presented are based on the measurements performed.

Speaker: Lawrence Soung Yee (Universite catholique de Louvain)

Paper http://iopscience.iop.org/1748-0221/7/12/C12028

Slides SoungYee_twepp12.pdf

11:35 Vertically Integrated Circuits for Detectors at Fermilab

The paper reviews the advancements in the three-dimensional integration of circuits for readout of solid-state detectors. It focuses on the details of the first 3D MPW run submitted in the HEP community. New high density circuit bonding techniques, wafer thinning, and submicrometer size TSVs IC provide new opportunities for a detector designer. These opportunities will be presented by looking at various 3D designs indicating that the 3D-IC technology is a reality. However, the problems manifested in the first MPW run, will not be forgotten and will be discussed in detail.

Speaker: Mr Ray Yarema (FNAL)

Paper http://iopscience.iop.org/1748-0221/8/01/C01052

Slides TWEEP2012_Oxford.pdf TWEEP2012_Oxford.pptx

12:00 Prototype Test Results of the Data Handling Processor for the DEPFET Pixel Vertex Detector.

In the new Belle II detector, which is currently under construction at the Super-KEKB e+/e- collider, two additional pixel layers using the DEPFET technology will be introduced- to improve the vertex reconstruction in the high luminosity environment. The Data Handling Processor chip, which is directly bump bonded to the silicon of the DEPFET modules, is designed to steer the readout process, pre-process and compress the data. Latest test results of prototype chips, including the data processing quality, the integrity of the transmission line and SEU cross sections for storage cells will be presented here.

Speaker: Mikhail Lemarenko (Universitaet Bonn (DE))

Paper http://iopscience.iop.org/1748-0221/8/01/C01032

Slides TWEPP2012_Lemarenko.pdf

11:10 → 12:25 B1b: Optoelectronics and Links

Convener: Francois Vasey (CERN)

11:10 The design of an optical link for the ATLAS Liquid Argon Calorimeter upgrade

We present the design of an optical link for the ATLAS liquid argon calorimeter upgrade. Challenging requirements are high data bandwidth (over 150 Gb/s raw data rate per board), radiation tolerance, low power consumption, high reliability, and low transmission latency. We discuss the link system design and component developments, especially those for the transmitting side that has to operate in the radiation environment. This presentation also serves as a summary of a few other presentations that detail in a particular function block of this link.

Speaker: Tiankuan Liu (Southern Methodist University)

Slides Liu_TWEPP12.pdf

11:35 Laser and Photodiode Environmental Evaluation for the Versatile Link Project

We summarize the results obtained in a series of radiation tests of candidate laser and photodiode components for use in the Versatile Transceiver (VTRx), the front-end component of the Versatile Link. We have carried out radiation testing at a full spectrum of sources (neutrons, pions, gammas) and can now compare the results and show that the spectrum of components that meet the radiation tolerance requirements is rather large. In addition, devices have been operated in a high magnetic field to qualify them for use in (HL-) LHC detectors.

Speaker: Dr Jan Troska (CERN)

Paper http://iopscience.iop.org/1748-0221/8/02/C02053

Slides VL_environment_TWEPP2012_18sep12.pdf

12:00 The Versatile Transceiver: Towards Production Readiness

Detectors involved in the upgrade programme of the LHC will need high-speed optical links to transfer readout and control data. The link front-end will be based on a radiation tolerant opto-electronic module, the Versatile Transceiver (VTRx), developed under the Versatile Link project. In this contribution we present a test system and protocol to be used to verify the compliance of the VTRx modules to the specifications, and a Versatile Link demonstrator based on the VTRx and the Gigabit Link Interface Board. Finally, we introduce the Small Footprint VTRx which is being designed for the CMS Tracker upgrade.

Speaker: Csaba Soos (CERN)

Paper http://iopscience.iop.org/1748-0221/8/03/C03004

Slides Versatile_Transceiver_Towards_Production_Readiness.pdf Versatile_Transceiver_Towards_Production_Readiness.pptx

12:25 → 14:00 Lunch

14:00 → 14:45 P2: Radiation Tolerant Power Converter Controls for the LHC

Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))

14:00 Radiation Tolerant Power Converter Controls for the LHC

The Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is the world’s most powerful particle collider. The LHC has several thousand magnets, both warm and super-conducting, which are supplied with current by power converters. Precise magnetic fields are created, ensuring the correct conditions for beam operation. If the magnetic field is incorrect the beam will be affected and beam losses can occur: in cases this leads to the execution of an emergency dump of the energy stored in the circulating beam before the losses become unacceptable. As beam losses can also cause localised heating in magnets, a failure in magnet powering can also lead to the execution of an emergency discharge of energy stored in the magnetic circuits. Each power converter is controlled by a purpose-built electronic module called a Function Generator Controller (FGC). This hardware allows remote control of the power converter state, and forms the central part of a closed-loop control system where the power converter Voltage is set, based on the converter output current and magnet-circuit characteristics. Some power converters and FGCs are located in areas which are exposed to beam-induced ionizing radiation. There are numerous radiation induced effects, some of which lead to a loss of control of the power converter, directly impacting upon the accelerator’s availability. In 2015 and 2016, following the first long shut down, the LHC will re-start with higher intensity beams, and higher beam energy. This is expected to lead to a significantly increased rate of radiation induced effects in materials close to the accelerator. Recent radiation tests indicate that using the current FGC would lead to an unacceptable loss of availability of the machine. A new FGC known as the FGClite is being designed to work reliably in the radiation environment expected in the LHC tunnel in the post-LS1 era. This paper outlines the concepts of power converter controls for machines such as the LHC, and introduces the risks related to radiation effects on electronics. The FGClite project is then described, with its key concepts and challenges: aiming for high availability in a radiation field.

Speaker: Dr Benjamin Todd (CERN)

Paper http://iopscience.iop.org/1748-0221/7/11/C11012 twepp_2012_btodd_paper_1v2.pdf

Slides twepp_2012_btodd_presentation_0v6.pptx

14:49 → 16:30 A2: Trigger

Convener: Wesley Smith (University of Wisconsin (US))

14:49 The Upgrade of the ATLAS Level-1 Central Trigger Processor

The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors as well as other sources and makes the final Level-1 Accept (L1A) decision. Due to the increasing luminosity of the LHC and the growing demands of physics and monitoring placed on the ATLAS Level-1 trigger system, the current CTP has reached its design limits. Therefore and in order to provide some margin for future operation, the CTP will be upgraded during the LHC shutdown of 2013/14.

Speaker: Stefan Haas (CERN)

Paper http://iopscience.iop.org/1748-0221/8/01/C01049

Slides TWEPP2012_Phase-0_CTP_Upgrade.pdf

15:14 ATLAS Level-1 Calorimeter Trigger Upgrades for Phase I

The ATLAS Level-1 Trigger requires several upgrades to maintain physics sensitivity as the LHC luminosity is raised. One of the most challenging is the electron trigger, with a major development planned for installation in 2018. New on-detector electronics will be installed to digitise electromagnetic calorimetry signals, providing trigger access to shower profile information. The trigger processing will be ATCA-based, with each multi-FPGA module processing ~1 Tbit/s of calorimeter digits within the current 2.5 microsecond Level-1 Trigger latency limit. The presentation will address the system architecture and design, with status of current tests.

Speaker: Dr Weiming Qian (Rutherford Appleton Laboratory)

Paper http://iopscience.iop.org/1748-0221/8/01/C01039

Slides Qian_ATLAS_Level-1_Calorimeter_phase_1_upgrade_--TWEPP2012.pdf

15:39 CMS Level-1 Upgrade Calorimeter Trigger Prototype Development

As the LHC increases luminosity and energy, it will become increasingly difficult to select interesting physics events and remain within the readout bandwidth limitations. An upgrade to the CMS Calorimeter Trigger implementing more complex algorithms is proposed. It utilizes AMC cards with Xilinx FPGAs running in micro-TCA crate with card interconnections via crate backplanes and optical links operating at up to 10 Gbps. Prototype cards with Virtex-6 and Virtex-7 FPGAs have been built and software frameworks for operation and monitoring developed. The physics goals, hardware architectures, and software will be described in this talk. More details can be found in a separate poster at this conference.

Speaker: Pamela Renee Klabbers (University of Wisconsin (US))

Paper http://iopscience.iop.org/1748-0221/8/02/C02013

Slides Klabbers_TWEPP2012.pdf Klabbers_TWEPP2012.ppt

16:04 A level 1 tracking trigger for the super LHC

Many of the previous tracking triggers have been based on table lookups using content addressable memories. An alternative method is being developed that uses pairs of closely separated silicon sensors to incrementally find particle tracks. This system avoids a complicated memory lookup so it is fast enough to work as a level 1 trigger. We describe the readout and data processing architecture necessary for this trigger system.

Speaker: Marvin Johnson (FNAL)

Paper http://iopscience.iop.org/1748-0221/8/02/C02004

Slides TWEPP_Trigger.pdf

14:50 → 16:30 B2: Programmable Logic, design tools and methods

Convener: Magnus Hansen (CERN)

14:50 A Digitization Scheme of Sub-microampere Current Using a Commercial Comparator with Hysteresis and FPGA-based Wave Union TDC

A digitization scheme of sub-microampere current using a commercial comparator with adjustable hysteresis and FPGA-based Wave Union TDC has been tested. The comparator plus a few passive components forms a current controlled oscillator and the input current is sent into the hysteresis control pin. The input current is converted into the transition times of the oscillations, which are digitized with a Wave Union TDC in FPGA and the variation of the transition times reflects the variation of the input current. Preliminary tests show that input charges <25fC can be measured at >50M samples/s without a preamplifier.

Speaker: Dr Jinyuan Wu (Fermilab)

Paper http://iopscience.iop.org/1748-0221/8/01/C01019

Slides DigiSub_uA12talk.pdf DigiSub_uA12talk.pptx

15:15 The GANDALF 128-channel Time-to-Digital Converter

The GANDALF 6U-VME64x/VXS module has been developed to cope with a variety of readout tasks in nuclear physics experiments and is amongst others operated at the COMPASS experiment at CERN. Based on this platform, we present a 128-channel TDC which is implemented in a Xilinx Virtex-5 FPGA using the shifted-clock-sampling method. Compared to well-known FPGA designs based on delay-lines, usually comprising only few input signals, this concept permits the implementation of a large number of TDC channels with a mean time resolution of 77 ps in a single FPGA device.

Speaker: Maximilian Buchele (Albert-Ludwigs-Universitaet Freiburg (DE))

Paper http://iopscience.iop.org/1748-0221/8/01/C01016

Slides buechele_TWEPP_2012_2.pdf

15:40 Development and Implementation of Optimal Filtering in a Virtex FPGA for the Upgrade of the ATLAS LAr Calorimeter Readout

In the context of upgraded read-out systems for the Liquid-Argon Calorimeters of the ATLAS detector, modified front-end, back-end and trigger electronics are foreseen for operation at the High-Luminosity LHC. Accuracy and efficiency of the energy measurement and reliability of pile-up suppression are substantial when processing the detector raw-data in real-time. Several digital filter algorithms are investigated for their performance to extract energies from incoming trigger signals and for the needs of the future trigger system. The implementation of fast, resource economizing, parameter driven filter algorithms in a modern Virtex FPGA is presented.

Speaker: Steffen Staerz (TU Dresden)

Paper http://iopscience.iop.org/1748-0221/7/12/C12017

Slides 2012_TWEPP_Oxford.pdf

16:05 Field Programmable Gate Array Based Data Digitisation with Commercial Elements

One of the most important aspects of particle identification experiments is the digitisation of time, amplitude and charge data from detectors. These conversions are done mostly with Application Specific ICs (ASICs). However, the recent developments in Field Programmable Gate Array (FPGA) technology allow us to use commercial electronic components for the required Front-End Electronics (FEE) and do the digitisation in the FPGA. It is possible to do Time-of-Flight (ToF), Time-over-Threshold (ToT), amplitude and charge measurements with converters implemented in FPGA. We call this principle come & kiss: Use COMplex COMmercial Elements & Keep It Small and Simple.

Speaker: Dr Michael Traxler (GSI Helmholtz Centre for Heavy Ion Research)

Paper http://iopscience.iop.org/1748-0221/8/01/C01035

Slides 201209_twepp_come_and_kiss.pdf

16:30 → 17:00 Break

17:00 → 19:00 POSTERS: First Session

First Session

Convener: Mitch Newcomer (University of Pennsylvania)

17:00 A two-channel, 8-Gbps serializer ASIC for the ATLAS liquid argon calorimeter upgrade

We present a high-speed, low power serializer ASIC, LOCs2, for the ATLAS liquid argon calorimeter upgrade. The ASIC consists of two 8 Gbps serializer channels, each of which has a 16-bit parallel data input in LVDS and a serial data output in CML logic. The ASIC is designed and fabricated in a 0.25-um commercial silicon-on-sapphire CMOS technology which is suitable for the high energy physics front-end electronics applications.

Speaker: Datao Gong (Southern Methodist Univeristy)

Slides locs2poster.pdf locs2poster.pptx

17:01 An 8-channel Programmable 80/160/320 Mbit/s Radiation-Hard Phase-Aligner Circuit in 130 nm CMOS

The design of an 8-channel phase aligner is presented that is to be used in the GBTX chip for the LHC upgrade program. The circuit is able to align the phases of up to 8 parallel data streams to the GBTX transmitter clock so that the data can be serialized. The bit rate is programmable between 80, 160 or 320 Mbit/s. Data jitter up to ± 3•Tbit/8 can be tolerated without compromising the errorless operation. The phase-aligner has been designed as a radiation-hard circuit in a 130 nm CMOS technology.

Speaker: Filip Francis Tavernier (CERN)

Paper http://iopscience.iop.org/1748-0221/7/12/C12022

17:02 A CMOS Pixel Sensor with 4-bit Column-Level ADCs for the ILD Vertex Detector

A 48 × 64 pixels prototype CMOS pixel sensor integrated with 4-bit column-level, self triggered ADCs for the ILD vertex detector outer layers was developed and fabricated in a 0.35 µm CMOS process with a pixel pitch of 35 µm. The pixel concept combines in-pixel amplification with a correlated double sampling operation. The ADCs accommodating the pixel read out in a rolling shutter mode complete the conversion by performing a multi-bit/step approximation. The design was optimized for power saving at sampling frequency. Preliminary test results of the prototype will be shown.

Speaker: Dr FREDERIC MOREL (IPHC-UDS-IN2P-CNRS)

Paper http://iopscience.iop.org/1748-0221/8/01/C01007

Poster Poster_ID13.pdf

17:03 The Design of 8-Gbps VCSEL Drivers for the ATLAS Liquid Argon Calorimeter Upgrade

We present the design and the preliminary test results of LOCld1 and LOCld4, the VCSEL drivers fabricated in a commercial 0.25-um silicon-on-sapphire (SOS) CMOS process for the ATLAS liquid argon calorimeter upgrade. Because of the bandwidth limitation of the process, we use an active shunt peaking technique, multiple-stage amplification and a voltage higher than the nominal voltage to achieve the data rate up to 8 Gbps. LOCld1 is a single channel driver with a differential output, while LOCld4 has four channels with single-ended open-drain output. Drivers have the adjustable modulation and peaking strength.

Speaker: Futian Liang (University of Science and Technology of China; Southern Methodist University)

Paper http://iopscience.iop.org/1748-0221/8/01/C01031

Poster The Design of 8-Gbps VCSEL Drivers for the ATLAS Liquid Argon Calorimeter Upgrade

17:04 Multi-Gigabit Wireless data transfer at 60 GHz

A Millimeter Wave Chip for a possible upgrade of the ATLAS Fast Tracker is under development. The 60 GHz unlicensed frequency band is of particular interest for indoor point-to-point multi gigabit data transfer due to its very large amount of spectral bandwidth (7-9 GHz). The targeted data rate for the first prototype is 3 Gbps. In this talk the key building blocks will be described, the current status of the design and performance obtained in simulations (power consumption, noise, etc.) will be presented. The emerging 3-D technology implementation scenarios and its benefits will be discussed.

Speaker: Mr Hans Kristian Soltveit (Physikalisches Institut)

Poster TWEPP_2012_poster_bis.pdf

17:05 Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card

The Insertable B-layer is planned for the upgrade of the ATLAS at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back-compatible solution (via DSP) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.

Speaker: Riccardo Travaglini (Universita e INFN (IT))

Paper http://iopscience.iop.org/1748-0221/8/01/C01012

Poster Poster_travaglini.pdf

17:06 Laser Tests of the DEPFET Gated Operation

DEPFET is an active pixel particle detector, in which a MOSFET is integrated in each pixel, providing first amplification stage of readout electronics. Excellent signal over noise performance is provided this way. The DEPFET sensor is planned to be used as an inner pixel detector in the BELLE II experiment at electron-positron SuperKEKB collider in Japan. Gated operation of the DEPFET is a unique function which allows making sensor insensitive for incoming radiation for defined time interval. The charge previously integrated is saved and integration can continue afterwards. Laser tests of gated DEPFET operation will be presented.

Speaker: Jan Scheirich (Charles University (CZ))

Paper http://iopscience.iop.org/1748-0221/8/01/C01051

Slides Poster.pdf

17:07 Initial prototype design for the VIPRAM: Vertically Integrated Patten Recognition Associative Memory

Future LHC experiments demand greater speed and orders of magnitude more patterns from associative memory-based track finders. The scaling of current technology in 2D is unlikely to satisfy the scientific needs. New technology will be needed. 3D Vertical Integration not only provides more active silicon per unit area creating higher pattern density, but also permits geometrical reconfiguration of the pattern finding function, reducing interconnect lengths and delays. The VIPRAM concept has been presented before, and is almost an ideal application for 3D. In this talk, we will present the design and test methodology as well as the prototype design.

Speaker: Jim Hoff (Fermilab)

Poster TWEPP_2012_Poster.pdf

Slides TWEPP_2012_Poster.pdf TWEPP_2012_Poster.pptx

17:08 Development of a Readout System for the PANDA Micro Vertex Detector

The Micro Vertex Detector (MVD) is the innermost tracking detector of the PANDA experiment at the upcoming FAIR facility in Darmstadt. The detector consists of several layers of silicon pixel and strip sensors to obtain precise tracking of charged particles. For the development of a front-end ASIC a flexible and powerful readout system was developed to interface different ASIC prototypes. We will present the upgrade of the FPGA-based Jülich digital readout system and measurements of the recent MVD pixel front-end prototype ToPix3. Tests of the implementation of the radiation hard GBT transfer protocol are also shown.

Speaker: Simone Esch (IKP, Forschungszentrum Jülich)

Paper http://iopscience.iop.org/1748-0221/8/01/C01043

Poster twepp2012.pdf

17:09 Testing and firmware development for the ATLAS IBL BOC prototype

For the coming upgrade of the ATLAS pixel detector at CERN a redesign of the current data readout is necessary. To communicate with the additional 448 front-end chips assembled in the Insertable B-Layer (IBL) new FPGA readout cards consisting of a Back of Crate card (BOC) and a Read Out Driver (ROD) have been developed. This paper will describe the firmware and hardware development of the new BOC prototype. Firmware tests, like electrical and optical loopback and communication tests with the new IBL front-end modules and the ROD will also be presented in the paper.

Speaker: Marius Wensing (Bergische Universitaet Wuppertal (DE))

Paper http://iopscience.iop.org/1748-0221/7/12/C12027

Poster TWEPP_Poster.pdf

17:10 A low-latency, low-overhead, quick resynchronization line code for the optical data links of the ATLAS liquid argon calorimeter upgrade

We propose a line code for the optical data links of the ATLAS liquid argon calorimeter upgrade. The line encoder inserts a frame trailer at the end of each data frame before the data are scrambled and the line decoder recovers the beginning and end of each frame, descrambles the data frame, and removes the frame trailer. The line code has low latency, low overhead, fast resynchronization capability and flexible frame size. Both the encoder and decoder have been implemented in an FPGA and the performance has been evaluated.

Speaker: Dr Tiankuan Liu (Southern Methodist University)

Poster Liu_TWEPP12_LOCic_poster_final.pdf

17:18 The Gigabit Link Interface Board (GLIB) ecosystem

The Gigabit Link Interface Board (GLIB) project is an FPGA-based platform for users of high-speed optical links in high energy physics experiments. The major hardware component is the GLIB Advanced Mezzanine Card (AMC). Additionally to the GLIB AMC, auxiliary add-on boards are under development in order to enhance the GLIB AMC I/O bandwidth and compatibility with legacy and future triggering and/or data acquisition interfaces. This article focuses on the development of the auxiliary cards that together with the GLIB AMC offer a complete solution for beam/irradiation tests of detector modules and optical links evaluation.

Speaker: Dr Paschalis Vichoudis (CERN)

Paper http://iopscience.iop.org/1748-0221/8/03/C03012

Slides GLIB_ecosystem_poster.v3.pdf

17:19 Temperature Characterization of Versatile Transceivers

The Versatile Transceiver is a part of the Versatile Link project, which is developing optical link architectures and components for future HL-LHC experiments. While having considerable size and weight constraints Versatile Transceivers must work in severe environmental conditions. One such environmental parameter is the temperature: the operating temperature range is specified to be from -30 to +60°C. In this contribution we present the results of the temperature characterization of the VTRx Transmitter (TOSA). Several TOSA candidates from different manufacturers have been characterized: single and multi-mode Vertical Cavity Surface-Emitting Lasers and a single-mode Edge-Emitter Laser.

Speaker: Lauri Juhani Olantera (CERN)

Paper http://iopscience.iop.org/1748-0221/8/03/C03007

Slides TWEPP12_Lauri_Olantera.pdf

17:20 Upgrade of the Cathode Strip Chamber Level 1 Trigger Optical Links at CMS

We present the results of initial tests of prototype optical links of an upgraded trigger for the Cathode Strip Chamber sub-detector at the CMS experiment at CERN. After presenting an overview of the existing system and upgrade requirements, we describe the hardware and firmware developed to drive the new links. Results of initial tests with the prototype Track Finder board and further plans are given in the conclusion.

Speaker: Mr Mikhail Matveev (Rice University)

Paper http://iopscience.iop.org/1748-0221/7/11/C11011

Poster LECC2012_poster.pdf

17:21 Irradiation tests on InP based Mach Zehnder Modulators

Particle detectors in High Energy Physics experiments, contain various types circuits and demand data rates of multiple Gbps per chip and several Tbps for the whole detector. Optical transmission by external modulation of a continuous wave laser is a possible solution to tackle the problem of high data rates.In this paper, we investigate the radiation hardness performance of InP-based Mach-Zehnder modulators. The modulator circuit is irradiated with a 24 GeV/c proton beam at CERN up to various fluences. Also, a design of an optical integrated circuit using the Generic Integration platform is presented.

Speaker: Deepak Gajanana (NIKHEF)

Paper http://iopscience.iop.org/1748-0221/8/02/C02025

Slides twepp2012_poster_photonics.pdf

17:22 Low-cost, high-precision propagation delay measurement of 12-fibre MPO cables for the CMS DT Electronics Upgrade

CMS DT electronics upgrade involves laying down 3500 optical links from the CMS cavern to the counting room, whose lengths must be matched to minimize skew, so that the present upstream electronics can be reused at an initial stage. In order to assess the cables’ compliance, a high resolution and cost-effective system has been developed to measure the length uniformity of these fibres. Transit-time oscillation method has been implemented with matched MPO 12-channel fibre optic transmitter and receiver and a Spartan-6 FPGA. After proper corrections and averaging, millimetre-range accuracy has been achieved.

Speaker: Alvaro Navarro Tobar (Centro de Investigaciones Energ. Medioambientales y Tecn. - (ES)

Paper http://iopscience.iop.org/1748-0221/8/02/C02001

Poster A_Navarro_TWEPP12.pdf

17:23 CuOF : an electrical to optical interface for the upgrade of the CMS Muon Drift Tubes system

The upgrade of the Drift Tube system of the CMS experiment foresees the relocation of the Sector Collector from the cavern to the counting room. It is thus required to convert the signals from electrical to optical, for a total number of 3500 channels running up to 480 Mb/s. A Copper to Optical Fiber (CuOF) board is currently under design. The board is divided into a mother board, which hosts the FPGA-based slow control system, and four mezzanine cards, each with 8 conversion channels. A prototype of the mezzanine board has been designed and tested under irradiation.

Speaker: Paolo De Remigis (INFN sez. di Torino)

Paper http://iopscience.iop.org/1748-0221/8/02/C02029

Poster deremigi.poster.pdf

17:24 The 120Gbps optical transmitter development for the High-Luminosity LHC (HL-LHC) experiments

The 120Gbps optical transmitter is a 12-channel, 10Gbps per channel, parallel pluggable module to operate on the detector front-end for the readout and control of High-Luminosity LHC (HL-LHC) experiments. We present the design concepts based on multiple TOSAs, precision array coupling and drop-in opto engines. We describe the prototype development and the experimental set-up for parametric testing. Several commercial optical transceivers and sub-components are investigated for the total dose and single event error effects. Possible power penalties in parallel transmission links are also explored in simulation and survey testing.

Speaker: annie xiang (Southern Methodist University)

Poster twepp12_acx_poster_v3.pdf

17:31 Triggerless Readout Architecture for the Silicon Pixel Detector of the PANDA Experiment

The readout architecture for the silicon pixel sensors of the PANDA MVD is presented.The pixel detector has to provide timing, position and energy information on a event-driven base, since no trigger signal is foreseen. The readout system is based on a custom ASIC, named ToPiX, directly connected to the GBT optical transceiver. A reduced size prototype with most of the main functionality has been designed and tested. The ASIC has been bonded to a sensor based on the epitaxial technology and tested on a beam test. Both TID and SEU tests on the ToPiX prototype have been performed.

Speaker: Giovanni Mazza (INFN sez. di Torino)

Paper http://iopscience.iop.org/1748-0221/8/02/C02017

Poster GMazza_TWEPP2012_ID001.pdf

17:32 Real Time Event Building for a Pixel Tracking Telescope Using an Advanced Mezzanine Card and MicroTCA

We have designed an advanced test-beam facility including a pixel tracking telescope. In the data path between the telescope and a PC, a commercial MicroTCA crate houses an Advanced Mezzanine Card (AMC) which receives, buffers, and processes the data from the tracking telescope, transmitting complete assembled events to the PC in real-time. This approach makes possible rapid assessment of the data and alignment and improves the efficient use of the beam. Recent test beam results using this approach will be reported.

Speaker: Mr Alan Prosser (Fermilab)

Poster TWEPP2012_uTCA_Poster_v3.pdf TWEPP2012_uTCA_Poster_v3.pptx

17:33 The ATLAS Pixel nSQP readout chain

The ATLAS Pixel new Service Quarter Panel (nSQP) project aims to deliver replacements for all on-detector services of the ATLAS Pixel Detector. The nSQPs will have LVDS transceivers at the place of the present electro-optical converters. The transceivers, realized in 130 nm technology, communicate with the existing ATLAS Pixel MCC chips, and over a 6.6m long electrical transmission line with VCSEL driver chips that are driving new electro-optical converters located in an accessible region. The talk will describe the development, performance and limitations of the electrical transmission lines, as well as quality assurance testing.

Speaker: Steven Welch (Oklahoma State University (US))

Slides TWEPP_Poster_-_Steven_Welch.pdf

17:34 The LHCb Silicon Tracker: Running experience

The LHCb Silicon Tracker is part of the main tracking system of the LHCb detector at the LHC. It measures very precisely the particle trajectories coming from the interaction point in the region of high occupancies around the beam axis. After presenting our production and comissioning issues in TWEPP 2008, we report on our running experience. Focusing on electronic and hardware issues as well as operation and maintenance adversities, we describe the lessons learned and the pitfalls encountered after three years of successful operation.

Speaker: Ms Sandra Saornil Gamarra (Universitaet Zuerich (CH) on behalf of LHCb Silicon Tracker group)

Paper http://iopscience.iop.org/1748-0221/8/02/C02027

Poster TWEPP2012_LHCbST_poster.pdf

17:35 Further Development of the MTCA.4 Clock and Control System for the EuXFEL Megapixel Detectors

The clock and control (CC) system for the EuXFEL megapixel detectors was presented in TWEPP 2011. It consists of a multipurpose MTCA.4 AMC card with an FPGA and a custom designed Rear Transition Module (RTM). This paper presents the experiences with the system since its first prototype and the development of the final hardware. Experiences with the hardware included the tests performed to evaluate the system functionality such as Front End Electronics (FEE) communication and the performance metrics such as the FEE clock jitter. The final version of the CC hardware along with the associated firmware are also presented.

Speaker: Sam Cook (University College London)

Paper http://iopscience.iop.org/1748-0221/8/01/C01017

Poster TWEPP_2012_poster.pdf

17:36 The PANDA MVD Strip Detector

The PANDA experiment at the future FAIR facility will study annihilation reactions of antiprotons. The Micro-Vertex-Detector as part of the tracking system will permit precise tracking and detection of secondary vertices. It is made of silicon pixel detectors and double-sided silicon strip detectors. Aspects of the development for the strip detector will be presented: Evaluation of prototype sensors as well as the readout chain, ranging from the front-end for the trigger-less readout concept of PANDA over the Module-Data-Concentrator ASIC at stave level to the off-detector electronics will be shown. Supported by BMBF.

Speaker: Mr Robert Schnell (HISKP, University Bonn; II. Phys. Inst., University Giessen)

Paper http://iopscience.iop.org/1748-0221/8/02/C02005

Poster PANDA_MVD_Strip_Detector.pdf

17:43 CMS Trigger Drift Tube Track Finder electronics upgrade Hardware Simulations

The upgrade of the Drift Tube Track Finder (DTTF) electronics will be designed using VHDL synthesis. The construction of the HDL structure merges improved blocks of the Track Finding algorithms and the results of the CMS wide detector control, monitoring and DAQ output common development. This merged design is subject of extended simulations both on behavioral level and concerning the timing constraints. The simulation results help in generating the complete design documentation.

Speaker: Janos Ero (Austrian Academy of Sciences (AT))

Slides 20120918_TWEPP_Oxford.pdf

17:44 An FPGA based topological processor prototype for the ATLAS Level-1 trigger upgrade

By 2014 the LHC will collide proton bunches at 14 TeV with an increased instantaneous luminosity up to 3×10^34cm−2s−1. A reduction on the trigger rate can be achieved by applying topological cuts adopting a new FPGA based module in the L1 trigger: the Topological Processor (TP). This presentation focuses on the design of the first TP prototype and on the test results on algorithm implemented in the TP demonstrator in order to measure latency and FPGA logic utilization.

Speaker: Volker Wenzel (Johannes-Gutenberg-Universitaet Mainz (DE))

Paper http://iopscience.iop.org/1748-0221/7/12/C12007

Poster poster_twepp2012.pdf

17:45 Instrumentation of a Level-1 Track Trigger at ATLAS with Double Buffer Front-End Architecture

The increased collision rate and pile-up produced at the HLLHC requires a substantial upgrade of the ATLAS level-1 trigger in order to maintain a broad physics reach. We show that tracking information can be used to control trigger rates, and describe a proposal for how this information can be extracted within a two-stage level-1 trigger design that has become the baseline for the HLLHC upgrade. We demonstrate that, in terms of the communication between the external processing and the tracking detector frontends, a hardware solution is possible that fits within the latency constraints of level-1.

Speaker: Ben Cooper (University College London)

Paper http://iopscience.iop.org/1748-0221/7/12/C12029

Poster AtlasTrackTrigger.pdf

17:46 The Upgrade of the PreProcessor System of the ATLAS Level-1 Calorimeter Trigger

The ATLAS Level-1 Calorimeter Trigger is a pipelined system to identify high-pT objects and to build energy sums within a fixed latency of ~2 us. It consists of a PreProcessor, which conditions and digitises analogue calorimeter signals, and two object-finding processors. The PreProcessor's tasks are implemented on a Multi-Chip Module, holding ADCs, time-adjustment and digital processing ASICs, and LVDS serialisers. A pin-compatible substitute, based on today's technology, like dual-channel ADCs and FPGAs, has been built to improve the BCID and pedestal subtraction algorithms. Test results with the first prototype are presented.

Speaker: Victor Andrei (Ruprecht-Karls-Universitaet Heidelberg (DE))

Paper http://iopscience.iop.org/1748-0221/7/12/C12026

Poster vandrei_PPrUpgr_poster.pdf

17:47 The Trigger System in the NEXT-DEMO detector

NEXT-DEMO is a large-scale prototype of NEXT, an experiment to search for neutrinoless double beta decays using a radiopure high-pressure gaseous xenon TPC with electroluminescence readout. Based on a PMT plane for energy measurements and a SiPM tracking plane for topological event filtering, front-end electronics, trigger and data-acquisition systems (DAQ) have been built. The DAQ is a low-scale implementation of the Scalable Readout System (RD51 collaboration). A reconfigurable hardware trigger system has been developed, allowing on-line triggering based on the detection of primary or secondary scintillation light, or a combination of both.

Speaker: Mr Raul Esteve (Universitat Politècnica de València)

Paper http://iopscience.iop.org/1748-0221/7/12/C12001

Slides Poster_TWEPP2012_final.pdf

17:48 the Optical Synchronization and Link Board project, oSLB

The calorimeter trigger synchronization of the Compact Muon Solenoid experiment at the large hadron collider (LHC) uses a synchronization method implemented in the synchronization and link board (SLB). The board allows the synchronization of electromagnetic and hadronic trigger primitives at the LHC frequency (40.08 MHz) and its transmission to the Regional Calorimeter Trigger. The new generation of the Calorimeter Trigger boards requires the usage optical links at a rate of 4.8Gb/s. The design options for the optical version of the oSLB as well the technological choices are presented.

Speaker: Mr Jose Carlos Da SIlva (LIP LISBON)

Paper http://iopscience.iop.org/1748-0221/8/02/C02036

Slides Poster_TWEPP12_rev.pdf

17:49 Multi-hundred Gbps processing boards for calorimeter trigger upgrades at CMS

Test results are presented for two AMC cards, the "CTP6" and "MP7", along with results from a custom Vadatech VT893 backplane. The two cards take different approaches to connectivity: one with fully-populated backplane connectivity and a 396Gbps asymmetric, optical interface, the other favouring, instead, a 1.4Tbps, symmetric, all-optical interface. The challenges of designing these cards necessitated the development of several test cards; the results of which are presented. An overview of the trigger upgrade project, including the physics motivations, the different architectures under consideration and the current status of prototypes, is presented in a separate talk at this conference.

Speaker: Dr Andrew William Rose (Imperial College Sci., Tech. & Med. (GB))

Poster TWEPP_POSTER_ANDREW_ROSE.pdf

20:00 → 22:00 Concert

Wednesday, 19 September

09:00 → 09:45 P3: Electronics for Neutrino Experiments

Convener: Ken Wyllie (CERN)

09:00 Electronics for Neutrino Experiments

Large non-collider experiments have special requirements for their electronics. Especially neutrino experiments have a large number of channels to read out the largest possible detector volume. The price per channel is often one of the design drivers, while at the same time having no dead time and 100% efficiency for the rare signal events. Data volume for these experiments is also often dominated by instrumental and other backgrounds. This paper will illustrate how different experiments are dealing with these challenges, their general readout philosophy from the front-end to the DAQ system and any special developments needed to achieve their objectives.

Speaker: Dr Alfons Weber (STFC/RAL)

Slides TWEPP-weber.pdf TWEPP-weber.pptx

09:45 → 10:35 A3a: Radiation tolerant components and systems

Convener: Christophe de La Taille (CNRS LAL Orsay)

09:45 Review of Rad Hard electronics activities at ESA

Many R&D activities are ongoing at European Space Agency to secure European industries competitiveness and non-dependence especially for what concerns EEE parts and avionics systems. Many synergies with experiences in astroparticle physics and in accelerator experiments exists, and will be presented and discussed. Future ESA flagship science mission targets the demanding Jupiter orbit, where radiation modelling, measurement and monitoring will be a key part of the mission, and new developments are necessary to overcome reliability, mass, power constraints that are difficult to met with current systems.

Speaker: Mr Gianluca Furano (European Space Agency)

Paper http://iopscience.iop.org/1748-0221/8/02/C02007

Slides RH_electronics_TWEEP_v3.pdf

10:10 First experience with radiation-hard active sensors in 180 nm HV CMOS technology

We explore the concept of using a deep-submicron HV CMOS process to produce a drop-in replacement for traditional radiation-hard silicon sensors. Such active sensors contain simple circuits, e.g. amplifiers and discriminators, but still require a traditional (pixel or strip) readout chip. This approach yields most advantages of MAPS (improved resolution, reduced cost and material budget, etc.), without the complication of full integration on a single chip. After outlining the design of the HV2FEI4 test ASIC, characterization results and first experience obtained with pixel and strip readout will be shown before discussing future prospects of active sensors.

Speaker: Daniel Muenstermann (CERN)

Slides Muenstermann_HV-CMOS.pdf

09:45 → 10:35 B3a: Systems, Planning, installation, commissioning and running experience

Convener: Ken Wyllie (CERN)

09:45 The Belle II Silicon Vertex Detector Readout Chain

The Silicon Vertex Detector of the future Belle II experiment at KEK (Japan) will consist of 6” double-sided sensors. Those are read out by APV25 chips (originally developed for CMS) which are powered by DC/DC converters with floating low voltages on top of the bias potentials. The signals are transmitted by cable links of about 12 meters. In the back-end, the data are digitized and processed by FADC modules with powerful FPGAs, which are also capable of precisely measuring the hit time of each particle in order to discard off-time background.

Speaker: Dr Markus Friedl (Austrian Academy of Sciences (AT))

Paper http://iopscience.iop.org/1748-0221/8/02/C02037

Slides 2012.09.19_belle2svdreadout_friedl.pdf 2012.09.19_belle2svdreadout_friedl.pptx

10:10 Ongoing electronic development in the CERN Beam Instrumentation Group: challenges and solutions for the measurement of particle accelerator beam parameters.

The Beam Instrumentation Group (BI) is responsible for designing, building and maintaining the instruments that allow observation of the particle beams and the measurement of related parameters for all CERN accelerators and transfer lines. This contribution is aimed to give an overview of the ongoing electronic developments within the beam instrumentation group both to improve the performances and ease the maintenance of instrumentation in the existing machines and to meet the requirements of future accelerators. Details on the some of the challenges and proposed technical solutions will be presented.

Speaker: Andrea Boccardi (CERN)

Paper http://iopscience.iop.org/1748-0221/8/03/C03006

Slides boccardi.pdf

10:40 → 11:10 Break

11:10 → 12:25 A3b: ASICS

Convener: Christophe de La Taille (CNRS LAL Orsay)

11:10 Radiation-Hard High-Speed Parallel Optical Links

We designed two optical-link ASICs for a new pixel layer of ATLAS. The ASICs include a 5 Gb/s driver for a 12-channel VCSEL array and a receiver/decoder to extract the data and clock from a 12-channel PIN array. The performance of the ASICs is satisfactory, including the ability to bypass broken PIN/VCSELs and set the ASICs to a default configuration with a power-on reset circuits in an event of communication failure. We will present results from the study, including results from irradiation and the design of a new 10 Gb/s VCSEL driver.

Speaker: Prof. Kock Kiam Gan (Ohio State University (US))

Paper http://iopscience.iop.org/1748-0221/7/12/C12025

Slides TWEPP2012_Gan.pdf

11:35 A 89dBΩ, 400Mhz transimpedance amplifier with improved radiation and temperature tolerance and 1:1600 dynamic range.

A chip is developed in a 130nm technology, containing a transimpedance amplifier with a 405MHz bandwidth, 89dBΩ transimpedance gain and a dynamic input range of 1:1600 for a photodiode capacitance of 0.75pF. The equivalent input noise is 216nA. The gain of the voltage amplifier, used in the TIA, degrades less than 3% over a temperature range from −40°C up to 125°C. The transimpedance-bandwidth product of the TIA equals 12THzΩ and has a simulated radiation tolerance larger than 1MGy degrading only 7% and 8.5% over the entire temperature range (-40 up to 125°C).

Speaker: Jens Verbeeck (K.U. LEUVEN)

Paper http://iopscience.iop.org/1748-0221/8/02/C02052

Slides twepp2012_jv.pdf (Protected) twepp2012_jv.pptx (Protected)

12:00 The GBLD : a radiation tolerant laser driver for high energy physics applications.

The GigaBit Laser Driver (GBLD) is a radiation tolerant ASIC which is part of the GigaBit Transceiver (GBT) chip-set. It is aimed to drive both edge emitting and VCSEL laser diodes at a data rate in excess of 5 Gb/s. The GBLD can provide a modulation current up to 24 mA and a bias current up to 43 mA.Pre- and de-emphasis functions are implemented to compensate for high external capacitive loads and asymmetric laser response. The chip is designed in a 130 nm CMOS technology and is powered by a single 2.5 V supply.

Speaker: Giovanni Mazza (INFN sez. di Torino, Italy)

Paper http://iopscience.iop.org/1748-0221/8/01/C01033

Slides GMazza_TWEPP2012_ID106.pdf

11:10 → 12:25 B3b: Systems, Planning, installation, commissioning and running experience

Convener: Ken Wyllie (CERN)

11:10 Jitter impact on clock distribution in LHC experiments

The quality of the 40MHz Bunch Clock distributed to the front-end electronics of the LHC experiments is one of the most classical questions discussed within electronics and applied physics communities. Jitter and phase-noise are complex concepts, composed of numerous sub-categories which can variously impact systems. This paper will deal with jitter and phase-noise, specifically applied to LHC bunch clock distribution system (TTC). Relation between constraints set by experiments and jitter type (cycle-to-cycle, TIE, phase noise) will be established. Finally, these values will be put into perspective by comparing them to the LHC beam characteristics.

Speaker: Mrs Sophie Baron (CERN)

Paper http://iopscience.iop.org/1748-0221/7/12/C12023

Slides Jitter_in_LHC_experiments_-_TWEPP12.pdf Jitter_in_LHC_experiments_-_TWEPP12.pptx

11:35 The AMC13 Module: A Common Solution for Clock, Controls and DAQ Services in CMS MicroTCA Systems

We have developed a custom MicroTCA module which provides timing, control, trigger and data acquisition functions in a MicroTCA crate for CMS experiment upgrades. This module mounts in the redundant MCH slot in a MicroTCA crate, and distributes LHC RF clock and encoded fast timing signals to 12 AMC modules. Data are collected from AMC modules using a MicroTCA fabric and transmitted to the CMS central DAQ on optical fibers at 5.0~Gbit/s. We describe the design of the AMC13 and results from installation at point 5 and operation in parasitic mode in the hadron calorimeter at CMS.

Speaker: Eric Shearer Hazen (Boston University (US))

Slides Hazen_B3B_AMC13.pdf

12:00 Recent developments for the Upgrade of the LHCb readout system

The LHCb collaboration has chosen to evaluate the ATCA architecture as form-factor for the LHCb readout system. A same board can satisfy all the requirements for data transmission, timing and fast control as well as slow control. First developments rely on a generic ATCA carrier board equipped with four dense AMC mezzanine able to interface a total of 144 bidirectional optical links at up to 10 Gbits/s. Early results and measurements will be presented.

Speaker: Jean-Pierre Cachemiche (Universite d'Aix - Marseille II (FR))

Paper http://iopscience.iop.org/1748-0221/8/02/C02014

Slides CPPM_Developments.pdf

12:25 → 14:00 Lunch

14:00 → 14:45 P4: Emerging Research Topics in Advanced Solid-State Image Sensors

Convener: Luciano Musa (CERN)

14:00 Emerging Research Topics in Advanced Solid-State Image Sensors

The impressive advancements in CMOS technologies over the last few decades have resulted in image sensors being a ubiquitous part of everyday life. However, there are always new challenges keeping research alive in the field of solid-state image sensors, with an increasing demand for imaging systems able to provide extra-information with respect to the standard digital cameras output. Among them there is the continuous progress of Single-Photon Avalanche Diode (SPAD) fabricated using standard CMOS technologies, which allow adding more and more, processing features onto the same chip while the pixel dimensions are shrinking. This kind of sensors, capable of resolving the photons time-of-arrival on a sub-nanosecond time scale, can be exploited in life science research for real-time fluorescence lifetime imaging and positron emission tomography. Another hot-topic, nowadays emerging in consumer market applications, concerns scannerless three-dimensional imaging, where a new class of sensors capable of measuring both the intensity map and the depth map of a scene is needed. Finally, a recently emerging challenge is the extension of the detectable frequency spectrum beyond the visible range, getting closer to the radio waves range in the so-called Terahertz region where the properties of the radiation become extremely interesting for many applications. In this talk, recent developments achieved on these topics worldwide and at FBK will be presented and discussed.

Speaker: David Stoppa (Fondazione Bruno Kessler – FBK)

Slides TWEPP_FBK_2012_Final.pdf TWEPP_FBK_2012_Final.pptx

14:50 → 16:05 A4: ASICS and Packaging & Interconnects

Convener: Luciano Musa (CERN)

14:50 Origami Chip-on-Sensor Design: Progress and New Developments

The Belle II SVD will consist of four layers of double-sided silicon detectors, arranged in ladders. Each sensor will be read out individually by utilizing the Origami chip-on-sensor concept, where the APV25 chips are placed on flexible circuits, glued on top of the sensors. Beside a best compromise between low material budget and sufficient SNR, this concept allows efficient CO2 cooling of the readout chips by a single cooling pipe per ladder. We present recent developments and improvements of the Origami concept as well as results of beam and cooling tests performed with prototypes at CERN.

Speaker: Mr Christian Irmler (HEPHY Vienna)

Paper http://iopscience.iop.org/1748-0221/8/01/C01014

Slides twepp2012_irmler.pptx

15:15 Design and characterization of a radiation-tolerant wide dynamic-range DC coupled and double polarity charge-to-digital converter for ionization chambers and diamond detectors

The design is based on charge-to-frequency conversion, with the addition of a new system to reconfigure the front-end - depending on the input signal level to increase the dynamic range at constant sampling frequency. The ASIC has been designed in 0.25 μm radiation tolerant CMOS technology aiming to cover a dynamic range of six decades with a 25kHz sampling rate: design, simulation and measurements are presented.

Speaker: Giuseppe Guido Venturini (Ecole Polytechnique Federale de Lausanne (CH))

Slides TWEPP2012.pdf

15:40 A Radiation-Hard PLL for Frequency Multiplication with Programmable Input Clock and Phase-Selectable Output Signals in 130 nm CMOS

A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320 MHz as a reference and generates clocks at the same frequencies, regardless of the input. Moreover, the outputs are available with a phase resolution of 90° for the 40, 80 and 160 MHz output and 22.5° for the 320 MHz output. The radiation-hard design, integrated in a 130 nm CMOS technology, is able to operate at a supply voltage between 1.2 V and 1.5 V.

Speaker: Filip Francis Tavernier (CERN)

Paper http://iopscience.iop.org/1748-0221/7/12/C12014

Slides TWEPP2012_ePLL.pdf TWEPP2012_ePLL.pptx

14:50 → 16:05 B4: Systems, Planning, installation, commissioning and running experience

Convener: Emilio Petrolo (Universita e INFN, Roma I (IT))

14:50 ATLAS Transition Radiation Tracker (TRT) Electronics Operation Experience at High Rates

The ATLAS Transition Radiation Tracker (TRT) is the outermost of the three subsystems of the ATLAS Inner Detector. ATLAS is one of two general‐purpose detectors built for the Large Hadron Collider at CERN. The TRT front‐end electronics use two custom‐built, radiation‐hard ASICs: the analog Amplifier, Shaper, Discriminator, Baseline Restorer (ASDBLR) chip and the Digital Time Measurement, ReadOut Chip (DTMROC). We report on how these chips performed during the ATLAS 2011 run where the TRT experienced much higher rates than previously encountered.

Speaker: James David Degenhardt (University of Pennsylvania (US))

Slides Degenhardt_TWEPP_Sept_2012_v5.pdf

15:15 In-beam experience with a highly granular DAQ and Control network: TrbNet

Many modern DAQ systems deploy a network running a custom network protocol to connect many FPGAs distributed on the detector. Key aspects are low latency, high bandwidth and also fault-tolerance. Another aspect is the control and monitoring system for the full detector. For the HADES experiment, the TrbNet protocol was developed to meet all of these requirements. The complete system is designed to be compatible with other detectors (e.g. CBM / PANDA @ FAIR) and table-top experiments. We are going to show the system architecture and network features as well as in-beam experience from our 2012 experimental run.

Speaker: Jan Michel (Goethe University Frankfurt)

Paper http://iopscience.iop.org/1748-0221/8/02/C02034

Slides JanMichel_HadesTrbNet.pdf

15:40 Research of long distance clock distribution system

The ARA project requires precision clock synchronization in electronic waveform capture circuits deployed in separate 200 m boreholes at the South Pole. Simultaneously digitized data must be transferred to trigger and readout electronics at the surface. We have tested two methods of embedding the clock distribution and recovery into the communications system: one using 4 LVDS pairs in CAT5 cable to transfer a 10MHz clock and 80Mbps data separately, the other using optical fiber to transfer 1.25 Gbps data and a 125MHz clock. Skew jitter between original and received clocks is less than 50 ps in both systems.

Speaker: Dr Yifan Yang (iihe)

Paper http://iopscience.iop.org/1748-0221/8/03/C03002

Slides Research_of_long_distance_clock_distribution_system.pdf Research_of_long_distance_clock_distribution_system.ppt

16:05 → 16:35 Break

16:35 → 18:35 WG 1: Micro-electronics User Group

Convener: Kostas Kloukinas (CERN)

16:35 News on foundry access services via CERN

Speaker: Kostas Kloukinas (CERN)

Slides MUG_TWEPP2012_intro_Kloukinas.pdf MUG_TWEPP2012_intro_Kloukinas.pptx

16:45 65nm technology: Design tools and foundry access services plans

Speaker: Sandro Bonacini (CERN)

Slides MUG-public.pdf MUG-public.pptx

17:15 - Open discussion with emphasis on 65nm technologies

16:35 → 18:35 WG 2: Optoelectronics Working Group

Conveners: Francois Vasey (CERN), Jingbo Ye (Southern Methodist University (US))

16:35 Active opto devices: have we reached their radiation tolerance limits?

Speaker: Jan Troska (CERN, Geneva, Switzerland)

Slides RadLimits_OptoWG_TWEPP2012_19sep12.pdf

17:05 Packaging opto components: how much can we do ourselves?

Speaker: Anthony Weidberg (University of Oxford (GB))

Slides

• Packaging_opto_components_opto_WG_2012.pdf
• Packaging_opto_components_opto_WG_2012.pptx
• SMU_TWEPP12_optoWG_ATx.pdf

17:35 Opto ASICs: where in the experiments can we safely use COTS?

Speaker: Annie Chu Xiang (Southern Methodist University (SMU))

Slides

• opto-asic-cots.pdf
• SMU_TWEPP12_optoWG_COTS.pdf
• Twepp_Opto_Working_Group_ANL.pdf
• Twepp_Opto_Working_Group_ANL.ppt

18:05 Opto ASICs: Will we be able to design 10G arrays?

Speaker: Prof. Kock Kiam Gan (Ohio State University (US))

Slides Opto_WG.pdf SMU_TWEPP12_optoWG_driverarray.pdf

16:35 → 18:35 WG 3: Power Working Group

Convener: Magnus Hansen (CERN)

16:35 Introduction

Speaker: Magnus Hansen (CERN)

Slides Power_WG_introduction_20120919.pdf Power_WG_introduction_20120919.pptx

16:45 Serial power & DCDC poster introduction

Speaker: Peter Phillips (STFC - Science & Technology Facilities Council (GB))

Slides 190912_PWG_2.pptx

17:00 Pulsed Power introduction

Speaker: christophe de La Taille (CNRS LAL Orsay)

Slides cdlt_twepp2012.pdf cdlt_twepp2012.ppt

17:30 Pulsed Power system issues

Speaker: Peter Goettlicher (Deutsches Elektronen-Synchrotron (DE))

Slides TWEPP_2012_power_cycling.pdf TWEPP_2012_power_cycling.pptx

17:50 Pulsed Power poster introduction

Speaker: Cristian Alejandro Fuentes Rojas (CERN)

Slides Cfuentes_19_09_2012_f.pdf Cfuentes_19_09_2012_f.ppt

18:00 AOB

16:35 → 18:35 WG 4: xTCA Working Group

Convener: Markus Joos (CERN)

16:35 Welcome

Speaker: Markus Joos (CERN)

Slides xtca_ig_5_opening_3.pdf xtca_ig_5_opening_3.pptx

16:40 Update on the MicroTCA transition in CMS

Speaker: Eric Shearer Hazen (Boston University (US))

Slides Hazen_xTCA_wg.pdf

16:55 The ATLAS VMEbus replacement project

Speaker: Markus Joos (CERN)

Slides ATLAS_VME_Replacement_xTCA_TWEPP12.pdf ATLAS_VME_Replacement_xTCA_TWEPP12.pptx

17:10 xTCA developments in Marseille for the LHCb Readout

Speaker: Jean-Pierre Cachemiche (Universite d'Aix - Marseille II (FR))

Slides CPPM_Developments_xTCA_IG.pdf

17:25 GLIB status update

Speaker: Paschalis Vichoudis (CERN)

Slides GLIB_2012.09.19_TWEPP-12.pdf GLIB_2012.09.19_TWEPP-12.pptx

17:35 News from the CERN PH-ESE xTCA evaluation project

Speaker: Stefan Haas (CERN)

Slides xTCA-Evaluation-TWEPP12.pdf

17:45 SRS in ATCA format

Speaker: Sorin Martoiu (Horia Hulubei National Institute of Physics and Nuclear Enginee)

Slides twepp_SRS-ATCA.pdf

Thursday, 20 September

09:00 → 09:45 P5: The AMS-02 electronics: design, production and qualification, in flight performance

Convener: Livio Mapelli (CERN)

09:00 The AMS-02 electronics: design, production and qualification, in flight performance.

The Alpha Magnetic Spectrometer (AMS-02) is a high-energy physics experiment designed to operate in space on board the International Space Station (ISS), where it has been installed on May 16th 2011, and is taking data continuously since then. Thanks to the very large acceptance (~ 0.5 m2 sr) and an exposure time of several years, AMS-02 will measure a wealth of data to study with unprecedented accuracy the composition and the energy spectrum of charged CRs and gammas up to the TeV energy scale. The instrument is made by five different subdetectors, for a total of ~ 300.000 channels, produces 7 GBit/sec of data, and use ~ 2 kW of electric power. The readout and DAQ electronics has been designed to obtain performances typical of HEP applications, within the constrains (power budget, QA/QC, radiation tolerance etc.) typical of a space application. We will review the whole project from the design and prototype phase, the production and qualification, the performance tests till the operation in space. In particular we will shown the very good performance of the system in the first year of operations.

Speaker: Giovanni Ambrosi (Universita e INFN (IT))

Slides 20120920_Ambrosi.pdf

09:50 → 10:40 A5a: ASICS

Convener: Mr Marcus Julian French (STFC - Science & Technology Facilities Council (GB))

09:50 SPACIROC2: A Front-End Readout ASIC for the JEM-EUSO observatory

The SPACIROC ASIC family is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). This rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which will equip the detection surface. Two main features of this ASIC are the photon counting mode for each input and the charge-to-time conversion for the multiplexed channels. SPACIROC1 was submitted in 2010 and showed global good behavior. A second version of SPACIROC has been designed to fix bugs and improve global consumption. Design and the test results of SPACIROC2 are presented in this paper.

Speaker: Ms Sylvie BLIN (Laboratoire de l'Accélérateur Linéaire)

Paper http://iopscience.iop.org/1748-0221/8/01/C01006

Slides 120920_twepp2012_SPACIROC2.pdf 120920_twepp2012_SPACIROC2.pptx

10:15 Ultra-Low-Power Radiation Hardened Analog to Digital Converter for Particle Detector Readout Applications

Radiation hardened analog to digital converter (ADC) has been designed for future high energy physics experiments. The ADC has been designed in a commercial 130nm CMOS process and it achieves 12-bit resolution,40 MS/s sampling speed, 15 mW power consumption and hardness to at least 1 Megarad(Si) of total ionizing dose (TID). 16 ADC channels will be placed on one packaged silicon chip. The ADC is a perfect match to the readout boards of the Liquid Argon Calorimeter of the ATLAS detector in the planned high-luminosity large hadron collider and to many other future experiments.

Speaker: Dr Esko Mikkola (Ridgetop Group, Inc.)

Paper http://iopscience.iop.org/1748-0221/8/04/C04007

Slides EMIKKOLA_TWEPP_2012.pdf EMIKKOLA_TWEPP_2012.pptx

09:50 → 10:40 B5a: Systems, Planning, installation, commissioning and running experience

Convener: Wesley Smith (University of Wisconsin (US))

09:50 Readout Electronics for the MicroBooNE LAr TPC, with CMOS Front-end at 89K

MicroBooNE experiment will use a ~100 ton LAr TPC detector to observe interactions of neutrinos from the on-axis BNB and off-axis NuMI Beam at Fermilab. The experiment will address the low energy excess observed by MiniBooNE experiment, measure low energy neutrino cross sections, and serve as the necessary next step towards massive LArTPC detectors. An overview of the front-end readout architecture of the MicroBooNE experiment will be presented. The design, prototypes and production of electronics system will be described. The results of extensive tests on the noise versus temperature and the uniformity of response will be presented.

Paper http://iopscience.iop.org/1748-0221/7/12/C12004

Slides Chen.MicroBooNE.09202012.pdf Chen.MicroBooNE.09202012.pptx

10:15 Development of the Scalable Readout System for Micro-Pattern Gas Detectors and Other Applications

Developed within RD51 Collaboration for the Development of Micro-Pattern Gas Detectors Technologies, the Scalable Readout System (SRS) is intended as a general purpose multi-channel readout solution for a wide range of detector types and detector complexities. The scalable architecture, achieved using multi-Gbps point-to-point links with no buses involved, allows the user to integrate different front-end ASICs and tailor the system size to his needs. Current applications include LHC upgrade activities or homeland security applications. The system architecture, development and running experience will be presented, together with future prospects, xTCA implementation options and application possibilities.

Speaker: Sorin Martoiu (Horia Hulubei National Institute of Physics and Nuclear Enginee)

Paper http://iopscience.iop.org/1748-0221/8/03/C03015

Slides twepp12_srs.pdf twepp12_srs.ppt

10:40 → 11:10 Break

11:10 → 12:25 A5b: ASICS

Convener: Mr Marcus Julian French (STFC - Science & Technology Facilities Council (GB))

11:10 VMM1 - An ASIC for Micropattern Detectors

We present a 64-channel ASIC designed for micropattern detectors. The ASIC discriminates and measures the amplitude and timing of events, including sub-threshold neighbors. With 200 pF input capacitance it provides charge resolution <5,000 electrons and sub-nanosecond timing resolution at 25 ns. The shaper, based on the concept of delayed dissipative feedback, gives an analog dynamic range in excess of 5000 at 200pF and 200ns. The discriminator, of new concept, can process sub-hysteresis amplitudes. The ASIC also provides sparse readout, trigger and address of the first event in real time, and direct timing outputs.

Speaker: Gianluigi De Geronimo (Brookhaven National Laboratory)

Slides VMM1_TWEPP2012_v8r.pdf VMM1_TWEPP2012_v8r.pptx

11:35 CALORIC: a Readout Chip for High Granularity Calorimeter

A readout chip has been developed to fulfil the requirements of the Si-W electromagnetic calorimeter of ILC. This electronics performs the complete processing of the signal: charge-sensitive amplification, synchronous shaping, analog memorization and digitization. Measurements show a global non-linearity better than 0.2% for low energy particles, and limited to 2% for high energy particles. The ENC is evaluated to 0.6 fC, which corresponds to a charge given by the MIP/6. With the timing sequence of the ILC, the power consumption of the complete channel is evaluated to 43uW thanks to the power pulsing.

Speaker: Mr Laurent Royer (IN2P3/Pôle MicRhau)

Paper http://iopscience.iop.org/1748-0221/8/02/C02051

Slides twepp_12_oxford_LR.pdf twepp_12_oxford_LR.pptx

12:00 Low Noise and Wide Dynamic Range Preamplifier and Shaper ASIC for the PANDA-Experiment

The ASIC design group at GSI developed a preamplifier and shaper ASIC which is optimized for the requirements of the electromagnetic calorimeter of the PANDA experiment. This integrated circuit will be used for spectroscopy and was designed for the readout of a large area APDs with 300pF detector capacitance, a very high dynamic range and an event rate of 350kHz. Each ASIC includes 2 equivalent readout channels consisting of a charge sensitive preamplifier, a three stage shaper and differential output buffers. The on chip implemented programmable voltage references are able to compensate the temperature dependency on the output DC.

Speaker: Peter Wieczorek (GSI Darmstadt, Germany)

Slides Contribution for TWEPP 2012

11:10 → 12:25 B5b: Systems, Planning, installation, commissioning and running experience

Convener: Wesley Smith (University of Wisconsin (US))

11:10 The TrainBuilder ATCA Data Acquisition Board for the European XFEL

The TrainBuilder is an Advanced Telecom ATCA data acquisition board being developed at the STFC Rutherford Appleton Laboratory to provide readout for the large 2D Mega-pixel detectors under construction for the European-XFEL in Hamburg. Each ATCA board can process ~8 GBytes/sec of raw detector data. The Train Builder system merges up to 5,120 partial detector images per second using FPGAs with DDR2 data buffers and an analogue crosspoint switch architecture. The Train Builder links operate with 10 Gigabit Ethernet protocols implemented in FPGA logic. The first TrainBuilder demonstrator boards were manufactured in April 2012.

Speaker: John Coughlan (STFC - Science & Technology Facilities Council (GB))

Paper http://iopscience.iop.org/1748-0221/7/12/C12006

Slides XFEL_TrainBuilder_slides_final.pdf XFEL_TrainBuilder_slides_final.ppt

11:35 The front-end electronics of the Spectrometer Telescope for Imaging X-Rays (STIX) on-board the ESA Solar Orbiter satellite

The front-end electronics design and interface to the data processing unit of the STIX X-ray spectrometer on the ESA Solar Orbiter satellite is presented. Solar Orbiter will be launched in 2017 to study sun/heliosphere interactions. STIX detects X-rays with Cadmium Telluride crystals in the energy range 4-150 keV. An ASIC (IdeF-X HD) with separate ADC is used for read-out. To achieve 1 keV FWHM resolution at 6 keV, cooling of the crystals to -20 deg C is necessary. This implies an electronics and mechanical design limiting the heat load to the cold unit.

Speaker: Oliver Grimm (ETH Zürich)

Paper http://iopscience.iop.org/1748-0221/7/12/C12015

Slides Talk-TWEPP2012-Grimm.pdf

12:00 Highly segmented electromagnetic Calorimeter prototype

A prototype of a highly segmented electromagnetic calorimeter has been developed. The detector tower is made of 24 layers of PHASE2/MIMOSA23 silicon sensors sandwiched between tungsten plates, with 4 sensors per layer, resulting in 39 MPixels in total. A detector readout and control system was developed, containing two Spartan 6 and one Virtex 6 FPGA, and running embedded Linux. In 550 ms 4 Gbytes of data is read from the detector and shipped to the DAQ system after readout via Gigabit ethernet.

Speaker: Dominik Fehlker (University of Bergen (NO))

Slides twepp12.pdf twepp12.ppt

12:25 → 14:00 Lunch

14:00 → 14:45 P6: Low-power High-Speed CMOS I/Os: Design Challenges and Solutions

Convener: Mitch Newcomer (University of Pennsylvania)

14:00 Low-power High-Speed CMOS I/Os: Design Challenges and Solutions

Due to the ever-increasing number of transistors on a processor chip, I/Os are more and more becoming the limiting factor on system performance. This presentation will describe the challenges for implementing the physical layer of high-speed wireline I/Os in CMOS in order to achieve both high data throughput and low power consumption. We will discuss how these goals can be met by proper choice of the system architecture, circuit topologies and equalization techniques such as the feed-forward equalizer (FFE), continuous time linear equalizer (CTLE), and decision-feedback equalizer (DFE). We will show examples of recent low-power implementations of transmitter and receiver circuits in CMOS operating at and above 28Gb/s. Looking further ahead, future ADC-based I/Os using digital equalizers will be discussed and compared to currently used analogue implementations.

Speaker: Mr Thomas Toifl (IBM Zurich)

Slides twepp_sept2012_final_v2.pdf

14:49 → 16:30 A6: Trigger

Convener: Emilio Petrolo (Universita e INFN, Roma I (IT))

14:49 Upgrade of the COMPASS calorimetric trigger

In 2009 COMPASS performed a test measurement of neutral Primakoff reactions, characterized by high energetic photons in one of the two electromagnetic calorimeters. Back then a digital trigger had been implemented to the existing readout electronics in order to detect these events. For 2012 a long measurement of these processes is foreseen. In order to extend the cinematic range to lower energetic photons the trigger system is upgraded in a way to be more selective to specific physics channels. In order to do so the hit information is combined and processed in one single FPGA.

Speaker: Stefan Huber (Technische Universitaet Muenchen (DE))

Paper http://iopscience.iop.org/1748-0221/8/02/C02038

Slides shuber_TWEPP2012.pdf

15:14 Performance of the AMBFTK board for the FastTracker Processor

Modern experiments at hadron colliders search for extremely rare processes hidden in much larger background levels. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. The FastTracker (FTK) processor for the Atlas experiment offers extremely powerful, very compact and low power consumption processing units for the far future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking. We report on the test results of the first prototype of the AMBFTK board assembled with a few prototypes of the AMchip04.

Speaker: Prof. Valentino Liberali (Università degli Studi di Milano)

Paper http://iopscience.iop.org/1748-0221/8/01/C01040

Slides presentationTWEPP12_Liberali.pdf

15:39 The ALICE EMCal L1 trigger first year of operation experience

The ALICE experiment at the LHC is equipped with an electromagnetic calorimeter (EMCal) designed to enhance its capabilities for jet measurement. In addition, the EMCal enables fast triggering on high energy jets and high pt photons with a multiplicity dependent threshold. After its commissioning in 2010, the EMCal L1 trigger has been officially approved for physics data taking in 2011. After describing the original Level 1 hardware and trigger algorithms, the commissioning and the first year of running experience, both in proton and heavy ion beams, are reviewed. Additionally, the needed upgrades to the original L1 trigger design are detailed.

Speaker: Olivier Raymond Bourrion (Centre National de la Recherche Scientifique (FR))

Paper http://iopscience.iop.org/1748-0221/8/01/C01013

Slides STU_talk.pdf

16:04 Status of the NA62 liquid krypton electromagnetic calorimeter level 0 trigger processor

The NA62 experiment at the CERN SPS aims to measure the Branching Ratio of the very rare kaon decay K+ -> pi+ nu nubar collecting ~100 events with a 10% background in two years of data taking. To reject the K+ -> pi+ pi0 background the NA48 liquid krypton calorimeter will be used in the 1-10 mrad angular region. A vertical slice of the trigger processor has been assembled and tested in the laboratory and is currently being installed at CERN SPS. Test results of a vertical slice of the NA62 liquid krypton electromagnetic calorimeter Level 0 trigger processor are presented.

Speaker: Andrea Salamon (INFN Sezione di Roma Tor Vergata)

Paper http://iopscience.iop.org/1748-0221/8/02/C02054

Slides twepp2012.salamon.pdf

14:50 → 16:30 B6: Power, grounding and shielding

Convener: Magnus Hansen (CERN)

14:50 A complete DCDC converter ASIC for LHC upgrades

A new and complete DCDC converter ASIC prototype has been designed and manufactured in a commercial 0.35um CMOS technology. The circuit is aimed at applications in LHC upgrades, where it can function in the intense magnetic field and survive to the radiation environment of even the trackers. Rated for an input voltage up to 10V, it provides a selectable output voltage and embeds under-voltage, over-temperature and over-current protections as well a soft-start to prevent excessive inrush current at startup. The characteristics of the ASIC are described, and first electric and radiation tests are presented.

Speaker: Stefano Michelis (CERN)

Slides michelis_draft.pdf michelis_draft.pptx

15:15 Design of a New Front-End Switching Power Supply

We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS Hadron Tile Calorimeter. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is in progress, and we present preliminary results from the production checkout.

Speaker: Gary Drake (Argonne National Laboratory)

Paper http://iopscience.iop.org/1748-0221/8/02/C02032

Slides 120920_TWEPP_drake_atlas_tilecal_lvps.pdf

15:40 A DC-DC conversion powering scheme for the CMS pixel detector upgrade

CMS has adapted a DC-DC conversion powering scheme for its phase-1 pixel upgrade, to be able to deliver the required amount of power with the existing cable plant. The presentation will focus on aspects that are relevant for the integration of DC-DC buck converters into a detector system. New measurements based on a full-scale prototype ASIC (AMIS4, CERN PH-ESE) will be presented, including the cooling performance with a CO2 system, reliability at low temperature, studies of potential frequency locking between DC-DC converters, and system tests with many DC-DC converters and several pixel modules.

Speaker: Katja Klein (Rheinisch-Westfaelische Tech. Hoch. (DE))

Paper http://iopscience.iop.org/1748-0221/8/02/C02024

Slides KatjaKlein_TWEPP12_20092012.pdf KatjaKlein_TWEPP12_20092012.pptx

16:05 Simulations and Measurements for a Concept of Powering CALICE-AHCAL at a Train-cycled Accelerator

To build homogeneous high granularity calorimeters low power consumption per channel is essential. Linear e+e- collider design duty cycles foresee bunch delivery over short periods, 1ms, followed by long, 200ms, breaks. Power cycling frontend electronics can reduce power consumption by a factor 100. For a full scale CALICE-AHCAL switched currents reach kilo Amperes magnitudes. This talk describes the design chain from frontend PCB’s through to external power supplies. By simulations a concept is developed, in which effects of electromagnetic interferences are kept small and localized. Long detector units will be available soon and first measurements are presented.

Speaker: Peter Goettlicher (Deutsches Elektronen-Synchrotron (DE))

Paper http://iopscience.iop.org/1748-0221/8/01/C01054

Slides TWEPP_2012_CALICE.pdf TWEPP_2012_CALICE.pptx

16:30 → 17:00 Break

17:00 → 19:00 POSTERS: Second Session

First Session

Convener: Mitch Newcomer (University of Pennsylvania)

17:00 ASIC design in the KM3NeT Detector

In the KM3NeT project, the electronics required to control the PMTs and collect the signals is integrated in two ASICs: 1. Front-end mixed signal ASIC (PROMiS) and 2. Analog ASIC (CoCo) to control the feedback of the high voltage (HV) circuit. We discuss the two integrated circuits and their test results. The read out ASIC amplifies converts input charge to pulse width and delivers the information via LVDS signals. PROMiS communicates with the control electronics via an I2C bus. CoCo contains a low power regulator and the feedback of the High voltage generator.

Speaker: Deepak Gajanana (NIKHEF)

Paper http://iopscience.iop.org/1748-0221/8/02/C02030/

Slides twepp2012_poster_CoCo_PROMiS.pdf

17:01 A 0.18 μm CMOS Low-Power Radiation Sensor for UWB Wireless Transmission

We describe the design of a floating gate-based MOS sensor embedded in a read-out CMOS sensing element used as a radiation sensor. A maximum sensitivity of 1mV/rad is estimated up to 10krad. The paper shows the design of a microelectronic circuit that includes a sensor, an oscillator and modulator, which is now under fabrication. Given the small estimated area of the complete chip prototype, i.e. less than 1mm2, the IC can enable a large variety of applications for spot radiation monitoring systems (High-Energy Physics experiments might benefit of this concept).

Speaker: Alessandro Gabrielli (Universita e INFN (IT))

Paper http://iopscience.iop.org/1748-0221/7/12/C12019

Poster Poster.pdf

17:02 SPIROC: design and performance of a dedicated very front-end electronics for an ILC Hadronic CALimeter (HCAL) prototype with SiPM read-out

The SPIROC chip is a dedicated very front-end electronics to read out a prototype of the Analog Hadronic Calorimeter (AHCAL) equipped with Silicon Photomultiplier (SiPM) for ILC (International Linear Collider). A first prototype of SPIROC has been fabricated in 2007 and a second version in 2010. Many testbench and testbeam measurements have been performed showing a good overall behaviour. However some limitations have been encountered. A new version has been submitted in February 2012 to correct them and to improve the ASIC performances. After an exhaustive description of the ASIC, the performances will be presented in this paper.

Speaker: Selma Conforti Di Lorenzo (OMEGA/LAL/IN2P3/CNRS)

Paper http://iopscience.iop.org/1748-0221/8/01/C01027

Poster poster_Selma_Conforti_Di_Lorenzo.pdf

17:03 Very fast front end ASIC associated with multi anode PMT for a scintillating-fiber beam hodoscope

For developing a scintillating-fiber beam monitor, we have designed a front-end 16-Channels readout chip to be associated with PMTs in a 0.35 µm BiCMOS process. Each channel consists of one input current conveyor driving separately a current comparator for signal event detection and a charge-sensitive amplifier for signal charge measurement. The ASIC version 2 has brought significant improvements: larger input dynamic range, lower power consumption, lower noise and a better phase margin. System testing has shown achievements of 4 MHz beam rate. The main limitation comes from the PMTs which saturates at such a rate

Speaker: Mr Shiming Deng (IPNL)

Paper http://iopscience.iop.org/1748-0221/8/01/C01047

Poster poster_TWEEP2012_Shiming_version_final.pdf

17:05 CLARO-CMOS, an ASIC for single photon counting with PMTs, MCPs and SiPMs

An ASIC named CLARO-CMOS was designed for fast photon counting with MaPMTs, MCPs and SiPMs. The ASIC was realized in a .35 um CMOS technology, and has 4 channels, each with a fast amplifier and a discriminator. The main features of the design are the high speed of operation, aiming to completely eliminate the dead time at a 40 MHz event rate, and low power dissipation, around 1 mW/ch and below. The high speed of operation combines with low noise to give a very low jitter, down to 10 ps rms, enough for most TOF applications.

Speaker: Claudio Gotti (University of Firenze and INFN Milano Bicocca)

Paper http://iopscience.iop.org/1748-0221/8/01/C01029

Poster 201209_TWEPP_Oxford.pdf

17:06 Front End ASIC design for SiPM Readout

A Front End ASIC for the readout of Silicon Photo-Multipliers is presented with the following features: wide dynamic range, high speed, multi channel, low input impedance current preamplifier, low power (7mW per channel), DC coupled input with common mode voltage control and separated timing and charge signal output. A detailed description of the SiPM modeling and parameter extraction is also included allowing the emulation of the signal generated by different commercial devices in the design simulation stage. This prototype includes basic blocks for 3 channels with: preamplifier with two separate signal paths and fast current discriminator with digital output.

Speaker: Albert Comerma Montells (Universidad de Barcelona)

Paper http://iopscience.iop.org/1748-0221/8/01/C01048

Poster TWEPP2012.pdf

17:13 Production, measurement and simulation of a low mass flex cable for multi gigabit/s readout for the LHCb VELO upgrade.

The goal of this project is to examine the feasibility of data transmission up to ~5Gbit/s on a short (~60cm) low mass flex cable. These cables will be used for the readout of the upgraded vertex detector (VELO) of the LHCb experiment in high radiation and vacuum environment. We present a study of different transmission line geometries, the effect of using fine pitch (400μm) connectors, the use of grounded guard traces and via holes to suppress crosstalk and the effect of the line parameters in the data transmission. Time and frequency domain measurements and simulation will be presented.

Speaker: Edgar Lemos Cid (Universidade de Santiago de Compostela (ES))

Paper http://iopscience.iop.org/1748-0221/8/01/C01018

Poster Poster_TWEPP_2012_v2.pdf

17:14 Hybrid circuits for the CMS Tracker upgrade front-end electronics

The upgrade of the CMS tracker at the HL-LHC requires the design of new front-end modules to cope with the increased luminosity and to implement L1 trigger functionnality. The new modules under development are based on high density hybrid circuits with new flip-chip front-end ASIC, and are wire bonded to strip sensors and connected to a service board for the data transmission. The suitability of different substrate technologies considered for the design of the hybrids is discussed, aiming for a cost effective and reliable manufacturability of the CMS tracker modules.

Speaker: Georges Blanchot (CERN)

Paper http://iopscience.iop.org/1748-0221/8/01/C01041

Poster TWEPP-12_Poster_CMS_Hybrids_01.pdf

17:15 Developments in the Use of Micro-structured Silicon devices for Thermal Management of HEP Detectors

Microchannel cooling has been selected for the thermal management of the NA62 GTK detector. The baseline design is based on a 130 micron thick silicon microstructured plate spanning over the whole sensor surface. An alternative design, based on a "frame-like" geometry, is also under study. Experimental measurements detailing the performance of both configurations will be presented and compared. Further applications in connection with two-phase evaporative flows are presently under developments for the upgrades of the ALICE ITS and LHCb Velo detectors. Preliminary results about these new cases will also be discussed.

Speaker: Alessandro Mapelli (CERN)

Poster Mapelli_Poster.pdf

17:22 The Upgraded CMS Preshower High Voltage System

In March 2012 the high voltage system of the silicon-sensor-based CMS Preshower detector underwent a significant upgrade. In addition to a doubling of the number of power supplies, a new active distribution board was developed and installed. This new board provides much improved flexibility in the powering, necessary to cope with the expected evolution of the 4288 silicon sensors with radiation damage. It also provides an active measurement of the ~2200 HV “lines” that go to the detector, enabling fast identification/diagnosis of any anomalous currents and providing detailed knowledge of the sensor current evolution with time.

Speaker: Dr Paschalis Vichoudis (CERN)

Paper http://iopscience.iop.org/1748-0221/8/01/C01050

Poster HVPP_poster_A0_v6.pdf

17:23 A Serially Powered ATLAS Strip Tracker Stavelet with Improved Referencing Connections

The engineering challenges related to the supply of electrical power to future large scale detector systems are well documented. The ATLAS Upgrade Strip Tracker Community has previously presented results from two demonstrator stavelets, one serially powered and one built with DC-DC convertors. Both approaches have the potential to increase the efficiency of the powering system. At the time of writing, construction of a new serially powered stavelet is underway. This uses a revised bus tape layout which facilitates additional referencing connections, devised as a result of earlier work. The latest results from this stavelet shall be presented.

Speaker: Peter Phillips (STFC - Science & Technology Facilities Council (GB))

Poster A0L_TWEPP_v4.pdf

17:24 The CMS ECAL Barrel HV power supply

The CMS electro-magnetic calorimeter comprises 75848 scintillating lead tungstate crystals. 61200 crystals are contained in the ECAL Barrel section and these are readout by avalanche photodiodes (APD) with internal gain. The APD gain strongly depends on the bias voltage that, for a gain G=50, is around 400 V. In order to match the requirements for gain stability, the power supply voltage must be stable to within 0.01%. In this talk we describe our experience with the installed Barrel HV power supply system which has been used for data taking at the LHC since 2008.

Speaker: Alessandro Bartoloni (Universita e INFN, Roma I (IT))

Paper http://iopscience.iop.org/1748-0221/8/02/C02039/

Poster The_CMS_ECAL_Barrel_HV_system.pdf

17:25 Prototype linear voltage regulators for the ABC130 front-end chip

The power distribution systems in the ATLAS Inner Tracker Upgrade require linear voltage regulators on the front-end chips to be the last stages of the powering chain. In the paper we present two designs: a classical voltage regulator based on an NMOS transistor as the pass element and an LDO voltage regulator employing a PMOS device. Both prototype regulators have been implemented in the 130nm CMOS process and are foreseen to be integrated in the ABCN130 front-end chip. The designs as well as the pre- and post-radiation test results for both prototypes will be presented and discussed.

Speaker: Michal Bochenek (University of Pennsylvania (US))

Paper http://iopscience.iop.org/1748-0221/8/01/C01037

Poster Bochenek_TWEPP2012.pdf

17:26 Conducted and radiated noise distribution on Pt rod power network for CMS Tracker upgrade.

The next generation of CMS tracker system will have all DC-DC converters located inside the tracker volume.They will be connected together in each rod via common power network, which propagates this noise along the rod.This paper presents several conducted and radiated test results on a prototype of the Pt power network.Test results will show the implication of the DC-DC converter position and grounding topology on noise emission along the rod.The goal of this study is to gain insight into the noise distribution along the rod power bus to increase the immunity of FEE.

Speaker: Maria Cristina Esteban Lallana (Aragon Institute of Technology (ES))

Poster posterEMC_ID136.pdf

17:27 Power pulsing schemes for vertex detectors at CLIC

The precision requirements of the vertex detector at CLIC impose strong limitations on the mass of such a detector (<0.2 X0 per layer). To achieve such a low mass, ultra-thin hybrid pixel detectors are foreseen, while the mass for cooling and services will be reduced by implementing a power-pulsing scheme that uses the low duty cycle of the accelerator. The principal aim is to achieve significant power reduction without compromising the power integrity supplied to the FEE. Different power-pulsing schemes are proposed and their electrical features are discussed on the basis of simulations and measurements.

Speaker: Cristian Alejandro Fuentes Rojas (CERN)

Paper http://iopscience.iop.org/1748-0221/8/01/C01057

Slides CFuentes_Poster_Twepp2012_Final.pdf

17:34 Quality assurance and functionality tests on electrical components during the ATLAS IBL production

For the first ATLAS pixel upgrade scheduled in 2013 a new front-end chip generation (FE-I4) has been developed. The second version (FE-I4B) hosting two different solid-state sensor technologies (planar silicon and 3D silicon) has been produced to be built into a new pixel layer (the Insertable B-Layer, IBL). Prototypes of these assembled modules have been tested in laboratory and testbeam measurements before and after irradiation.

Speaker: Jennifer Jentzsch (Technische Universitaet Dortmund (DE))

Slides TWEPP_Poster_JJentzsch_final.pdf

17:35 A new portable test bench for the ATLAS Tile Calorimeter front-end electronics

This paper describes a new portable test bench for the TileCal sub-detector of the ATLAS experiment at CERN. The system is used for the certification and quality checks of the front-end electronics drawers. It is designed to be an easily upgradable version of the current 10-year-old system, able to evaluate the new technologies planned for the upgrade as well as provide new functionality to the present system. It will be used during the long shutdown of the LHC in 2013-14 and during future maintenance periods.

Speaker: Pablo Moreno (Universidad de Valencia)

Paper http://iopscience.iop.org/1748-0221/8/02/C02046

Slides twepp_2012_blue_v9.pdf

17:36 Production Test Engineering in FE-I4 System-on-Chip to boost the Reliability and High-Quality demands in IBL applications

The article addresses production test development effort of the ATLAS FE-I4 integrated circuit. This particular production test targets manufacturing faults in the ICs and has been taken as a supplementary approach, besides standard functional test, to decrease further the risk of potential application failures. The Design-for-Test structures inside the digital part of the chip together with the specially devised top-level simulations enabled straightforward test development and debug in the production test environment. The production test itself has been commissioned to the external test company, with the supervision of the FE-I4 team at the test floor.

Speaker: Vladimir Zivkovic (NIKHEF Institute)

Paper http://iopscience.iop.org/1748-0221/8/02/C02003

Poster Poster_ID90.pdf

17:43 New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC

In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled. In this upgrade, the inner detector of the ATLAS experiment will be replaced including the pixel detector. This new pixel detector requires a control system which complies with the strict requirements in terms of radiation hardness and material budget in ATLAS. The University of Wuppertal is developing a DCS (Detector Control System) network consisting of two kinds of ASICs: the DCS Chip and the DCS Controller. Both are manufactured in 130nm technology. We present results from measurements from new prototypes for the DCS network.

Speaker: Lukas Püllen (Uni-Wuppertal)

Paper http://iopscience.iop.org/1748-0221/8/03/C03019

Poster TWEPP_2012_A0.pdf

17:50 Development of a custom on-line ultrasonic vapour analyzer/flowmeter instrument for the ATLAS inner detector, with application to gaseous tracking and Cherenkov Detectors

Precision sound velocity measurements can simultaneously determine binary gas composition and flow. We have developed an ultrasonic analyzer with custom electronics, currently in expanding use within the ATLAS experiment, with numerous potential applications. The ATLAS silicon tracker compressor-based C3F8 evaporative cooling system will be replaced with a thermosiphon and may also circulate a blend containing 20-30% C2F6, for enhanced safety against thermal runaway at higher LHC luminosities. Central to these developments is a new speed-of-sound instrument for simultaneous measurement of flow and C3F8/C2F6 mixture. The custom microcontroller-based electronics and the instrument functionality are described.

Speaker: Sergey Katunin (B.P. Konstantinov Petersburg Nuclear Physics Institute (PNPI), 188300 St. Petersburg, Russia)

Paper http://iopscience.iop.org/1748-0221/8/01/C01002

Poster TWEPP_2012.pdf

17:51 New data acquisition system for the COMPASS experiment

The current data acquisition system (DAQ) of the COMPASS experiment at CERN uses the DATE package installed on standard x86 compatible server machines for event building. This system does not scale well with increasing data and trigger rates. Therefore we develop a new DAQ system that would perform detector readout and event building in a custom made FPGA based hardware. The software part would provide control and monitoring function. Currently prototypes of the new FPGA card are being tested and control monitoring software is prepared for tests with real hardware.

Speakers: Josef Novy (C), Martin Bodlak (Czech Technical University (CZ)), Vladimir Jary (Czech Technical University (CZ))

Paper http://iopscience.iop.org/1748-0221/8/02/C02009

Poster New Data Acquisition System for the COMPASS experiment

17:52 firmware approach for TEL62 trigger and data acquisition board

The main goal of the NA62 experiment at the CERN SPS is to measure the branching ratio of the ultra-rare K+ → π+νν decay, collecting about 100 signal events in 2 years. Readout uniformity of sub-detectors, scalability, efficient online selection and loss-less readout at high rate are key issues. The TEL62 is the principal block of the Na62 DAQ and his architecture is based on a star topology. Tel62 collects data coming from the sub-detectors, process and temporary stores them in a buffer extracting only the ones requested by the trigger system. The complete dataflow is described.

Speaker: Elena Pedreschi (Sezione di Pisa (IT))

Poster firmware_approach_for_TEL62_trigger_and_data_acquisition_board.pdf

17:53 Soft Error Recovery during Operation of the CMS Experiment

In high energy physics experiments such as the Compact Muon Solenoid (CMS), electronics located near the interaction region are prone to soft (i.e., recoverable) errors as a result of radiation coming from the collisions. Depending on the type of error, the scope of their impact on data collection can range from being hardly noticeable to being completely debilitating. Here, we present evidence of soft errors in CMS and describe a mechanism which allows subsystems to recover from them in an automated way. Results will be shown as to the effectiveness of this scheme to maximize the uptime of CMS.

Speaker: Gregory Rakness (Univ. of California Los Angeles (US))

Paper http://iopscience.iop.org/1748-0221/8/02/C02008

Poster Rakness_TWEPPposter_SoftErrorRecoveryduringOperationoftheCMSExperiment_20120920_Final.pdf

17:54 Mitigation of Anomalous APD signals in the CMS ECAL

We describe the observation and mitigation of anomalous, large signals, observed in the barrel part of the CMS Electromagnetic Calorimeter during proton collisions. Laboratory and beam tests, as well as simulations, have been used to understand their origin. They are ascribed to direct energy deposition by particles in the avalanche photodiodes used for light readout. A reprogramming of the front-end electronics has allowed a majority of these anomalous signals to be identified and rejected at the first (hardware) trigger level with minimum impact on physics performance. Further rejection is performed in the high-level (software) trigger and offline analyses.

Speaker: Wojciech Bialas (CERN)

Paper http://iopscience.iop.org/1748-0221/8/03/C03020

Poster TWEPP2012_DAP_WB_poster_final.pdf

17:55 The First G-APD Cherenkov Telescope (FACT) camera and its electronics - overview, operation experience and outlook

Within the FACT project, we constructed the first full-scale Cherenkov telescope camera based on Geiger-mode avalanche photodiodes (G-APDs). Compared to photomultipliers, G-APDs are more robust, need lower operation voltage and promise higher efficiency and lower cost. The FACT camera comprises 1440 pixels and readout channels, based on the DRS4 analog pipeline chip and features fully integrated electronics with commercial Ethernet components for data transfer. Since October 2011, the FACT camera is operational in the harsh outdoor environment at the Roque de los Muchachos Observatory. I will present the FACT camera electronics, results, operational experience and outlook.

Speaker: Mr Patrick Vogler (Institute for Particle Physics, ETH Zurich)

Poster TWEPP_Poster_v5.pdf

17:56 The NA62 Large Angle Veto front end electronic board

The NA62 experiment will measure the BR(K+->π+νν) to within about 10%. To reject the dominant background from photons, the large-angle vetoes (LAVs) must detect particles with < 1 ns time resolution and 10% energy resolution over a very large energy range. A low threshold, large dynamic range, Time-over-threshold based solution has been developed for the LAV front end electronics. Our custom 32 channel 9U board uses a pair of low threshold discriminators for each channel to produce LVDS logic signals. The achieved time resolution obtained in laboratory, coupled to an HPTDC based readout board, is ~150 ps.

Speaker: Dr Francesco Gonnella (LNF (IT))

Paper http://iopscience.iop.org/1748-0221/8/01/C01020

Slides gonnella_TWEPP_poster.pdf

17:57 Development of a readout link board for the TileCal phase 2 demonstrator

The ATLAS Tile Calorimeter phase 2 upgrade demonstrator aims at installing a hybrid on-detector electronic system replacing 1-4 adjacent TileCal drawers in ATLAS starting end of phase 0, combining a fully functional phase 2 system with circuitry making it compatible with the present system. We are reporting a second generation prototype link and controller board connecting the drawer to off-detector electronics in USA-15. The new boards main logic component is a XILINX Kintex7 FPGA connected to an 12x5 Gb/s AVAGO opto transmitter and a 4x10 Gb/s QSFP+ connector.

Speaker: Steffen Lothar Muschter (Stockholm University (SE))

Paper http://iopscience.iop.org/1748-0221/8/03/C03025

Poster TWEPP_Stockholm_University.pdf

17:58 A new Readout Control system for the LHCb Upgrade at CERN

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire readout architecture will be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and the first hardware implementation of a new Readout Control system for the LHCb upgrade. The system is based on FPGAs and bi-directional links for the control of the entire readout architecture. First results on the validation of the system are given.

Speaker: Federico Alessio (CERN)

Paper http://iopscience.iop.org/1748-0221/7/11/C11010

Slides 120919_Poster_TWEPP12.pdf

17:59 Readout system for high resolution resistive plate chambers

We describe our apparatus built to track cosmic muons using Resistive Plate Chambers (RPC). The system consists of 12 RPCs (50 cm X 50 cm) each one coupled with 330 strips (1.5 mm pitch) and readout by means of MAROC multiplexing chips. We also present the current version of the system, where the readout is implemented using ASICs. The new system is characterized by high modularity and uses the IPBus protocol for configuration of the boards and data readout. Each RPC module is a self triggering unit and all the communications with the central DAQ are performed over Ethernet.

Speaker: David Cussans (University of Bristol (GB))

Paper http://iopscience.iop.org/1748-0221/8/03/C03003

Poster Baesso_twepp2012_v4.pdf

18:00 Cold electronics for the LBNE LAr TPC

The LBNE Project is developing modular multi-kiloton liquid argon time projection chambers for the Long Baseline Neutrino Experiment. A complete electronic readout system operating in LAr for 20 years is essential to this design. We are developing 180 nm commercial technology CMOS ASICs, with low-noise readout of the TPC wires, digitization, zero-suppression, buffering and output multiplexing. An analog frontend is complete, and will be used in the MicroBooNE LArTPC. Prototypes of the digital section have been fabricated. Results demonstrate that CMOS transistors have lower noise and improved DC characteristics in LAr. We describe results and planned development.

Speaker: Craig Thorn (Brookhaven National Laboratory)

Poster Thorn_LBNE_Electronics_TWEPP_v2.pdf

18:01 Microcontroller based data acquisition system for silicon photomultiplier detectors.

Silicon photomultipliers are robust, low power detectors for low light levels. This, along with the low bias voltages and their relatively low cost makes them a good candidate for portable scintillation detectors. A data acquisition system based around a microcontroller has been developed for such a detector with a small number of data channels. Different powering and data recording or reporting options have been investigated for a range of possible operational scenarios such as laboratory based cosmic ray measurements, high altitude cosmic ray measurements and portable radiation detection.

Speaker: Nick Ryder (University of Oxford (GB))

Paper http://iopscience.iop.org/1748-0221/8/02/C02019

Slides ryderTWEPP12.pdf

19:30 → 23:00 Conference Dinner

Friday, 21 September

09:00 → 09:45 P7: Using reconfigurable FPGAs in radioactive environments: challenges and possible solutions

Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))

09:00 Using reconfigurable FPGAs in radioactive environments: challenges and possible solutions

Reconfigurable FPGAs are very appealing for mission critical applications where the capability of changing the hardware functionality on-the-fly (i.e., without expensive and time consuming maintenance operations) is a breakthrough. Space missions, as well as high energy physics experiments may benefit from the reconfiguration capability that modern FPGAs offer, but the designers have to face the daunting task of dealing with the effects of radioactive environments on FPGAs. In this talk, we will address the effects of radioactive environments on modern reconfigurable FPGAs from the perspective of application designers. Moreover, we will present possible countermeasures against radiation effects.

Speaker: Prof. Massimo Violante (Turin Politecnico)

Slides pres_mv_twepp_2012.pdf pres_mv_twepp_2012.pptx

09:45 → 10:35 Topical

Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))

09:45 FPGAs operating in a Radiation Environment: Lessons Learned from FPGAs in Space

Field Programmable Gate Arrays (FPGAs) are an attractive alternative to application specific integrated circuits (ASICs) because of their in-field reprogrammability, low non-recurring engineering costs (NRE), and relatively short design cycle. They provide high logic density, access to the latest I/O standards, and can be designed with a variety of low-cost tools. FPGAs are increasingly used in non-traditional applications such as harsh environments and in safety critical systems. Recently, there has been great interest in using FPGAs within spacecraft. FPGAs, like all semiconductor devices, are susceptible to the effects of radiation. The radiation effects of concern are single event effects (SEE). The large amount of memory within an FPGA required for specifying the circuit configuration is susceptible to single event upsets and transients. There is an active research community investigating the effects of radiation on FPGAs and developing methods to mitigate against these effects. There has been significant progress over the last decade in the understanding and development of FPGA technology that is resistant to the effects of radiation. The success of these efforts has allowed the use of FPGAs in many existing spacecraft systems. This presentation will summarize the effects of radiation on FPGAs, methods to mitigate against these effects, and provide case studies of successful FPGA systems operating in space.

Speaker: Dr Mike Wirthlin (Brigham Young University, Provo, Utah)

Paper http://iopscience.iop.org/1748-0221/8/02/C02020

Slides

• twepp_wirthlin_Sept_2012.pdf
• twepp_wirthlin_Sept_2012.ppt
• twepp_wirthlin_Sept_2012.ppt.pdf

10:10 First Results of Fault Injection Tests done to Study the Radiation Tolerance of the Readout Control FPGA Design of the ALICE TPC Detector

The ALICE Time Projection Chamber (TPC) is the main tracking detector of ALICE. In the Readout Control Unit (RCU) an SRAM based FPGA from Xilinx controls the read out of data from the detector. Functional failures due to single event upsets are possible in the SRAM configuration memory of the FPGA. This paper presents the results of fault injection tests that have been performed to systematically study how configuration memory bit flips will impact the failure frequency.

Speaker: Johan Alme (Bergen University College (NO))

Paper http://iopscience.iop.org/1748-0221/8/01/C01053

Slides TWEPP2012-j.alme.pdf TWEPP2012-j.alme.pptx

10:35 → 11:05 Break

11:05 → 11:55 Topical

Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))

11:05 Very Forward Muon Trigger and Data Acquisition Electronics for CMS: Design and Radiation Testing

With the forthcoming High Luminosity LHC accelerator upgrade, the CMS Endcap Muon system will require new electronics to handle the increased data rate while maintaining high data collection efficiency. Maintaining trigger efficiency for pseudorapidity above 2.1 requires deployment of higher performance electronics already in 2013. With the increased luminosity, the new electronics will be exposed to substantial radiation levels requiring higher tolerance of the components to radiation. We report on the progress in developing and building the new system and the results of radiation tolerance testing of the commercial components used in the system.

Speaker: Jason Gilmore (Texas A & M University (US))

Paper http://iopscience.iop.org/1748-0221/8/02/C02040

Slides TWEPP2012_CSCslides.pdf TWEPP2012_CSCslides.pptx

11:30 SEU tolerant latches design for the ATLAS pixel readout chip

The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches where layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. For the future pixel readout design, a prototype chip containing 512 pixels is implemented in a 65 nm CMOS process. SEU tolerant latches are implemented for the pixel configuration and the SEU tolerance is under test and evaluation.

Speaker: Mohsine Menouni (Universite d'Aix - Marseille II (FR))

Paper http://iopscience.iop.org/1748-0221/8/02/C02026

Slides TWEPP2012_FEI4chipforATLAS_V4.pdf TWEPP2012_FEI4chipforATLAS_V4.pptx

11:55 → 12:35 WGS: WG Summaries

Convener: Philippe Farthouat (CERN)

11:55 Opto Working Group

Speaker: Francois Vasey (CERN)

Slides TWEPPOptoWGRecap21Sep2012.pdf

12:05 xTCA Working Group

Speaker: Markus Joos (CERN)

Slides TWEPP2012_xTCA_IG_summary_joos.pdf TWEPP2012_xTCA_IG_summary_joos.pptx

12:15 Micro-electronics Working Group

Speaker: Kostas Kloukinas (CERN)

Slides MUG_TWEPP2012_wrap-up_Kloukinas.pdf MUG_TWEPP2012_wrap-up_Kloukinas.pptx

12:25 Power Working Group

Speaker: Magnus Hansen (CERN)

Slides Power_WG_summary_20120921.pdf Power_WG_summary_20120921.pptx

12:35 → 13:00 TWEPP-12 Close Out

Convener: Dr Todd Brian Huffman (University of Oxford (GB))

12:35 TWEPP-12 Close Out

Speaker: Philippe Farthouat (CERN)

Slides TWEPP12-Closing.pdf TWEPP12-Closing.pptx