TWEPP 2012 Topical Workshop on Electronics for Particle Physics

Session

Topical

TOP

21 Sept 2012, 09:45

Oxford University, UK

Conveners

Topical

• Geoff Hall (Imperial College Sci., Tech. & Med. (GB))

Topical

• Geoff Hall (Imperial College Sci., Tech. & Med. (GB))

159. FPGAs operating in a Radiation Environment: Lessons Learned from FPGAs in Space

Dr Mike Wirthlin (Brigham Young University, Provo, Utah)

21/09/2012, 09:45

Oral

Field Programmable Gate Arrays (FPGAs) are an attractive alternative to application specific integrated circuits (ASICs) because of their in-field reprogrammability, low non-recurring engineering costs (NRE), and relatively short design cycle. They provide high logic density, access to the latest I/O standards, and can be designed with a variety of low-cost tools. FPGAs are increasingly used...

63. First Results of Fault Injection Tests done to Study the Radiation Tolerance of the Readout Control FPGA Design of the ALICE TPC Detector

Johan Alme (Bergen University College (NO))

21/09/2012, 10:10

Oral

The ALICE Time Projection Chamber (TPC) is the main tracking detector of ALICE. In the Readout Control Unit (RCU) an SRAM based FPGA from Xilinx controls the read out of data from the detector. Functional failures due to single event upsets are possible in the SRAM configuration memory of the FPGA. This paper presents the results of fault injection tests that have been performed to...

145. Very Forward Muon Trigger and Data Acquisition Electronics for CMS: Design and Radiation Testing

Jason Gilmore (Texas A & M University (US))

21/09/2012, 11:05

Oral

With the forthcoming High Luminosity LHC accelerator upgrade, the CMS Endcap Muon system will require new electronics to handle the increased data rate while maintaining high data collection efficiency. Maintaining trigger efficiency for pseudorapidity above 2.1 requires deployment of higher performance electronics already in 2013. With the increased luminosity, the new electronics will be...

139. SEU tolerant latches design for the ATLAS pixel readout chip

Mohsine Menouni (Universite d'Aix - Marseille II (FR))

21/09/2012, 11:30

Oral

The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches where layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. For the future pixel readout design,...