Conveners
P6: Low-power High-Speed CMOS I/Os: Design Challenges and Solutions
- Mitch Newcomer (University of Pennsylvania)
Mr
Thomas Toifl
(IBM Zurich)
20/09/2012, 14:00
Due to the ever-increasing number of transistors on a processor chip, I/Os are more and more becoming the limiting factor on system performance. This presentation will describe the challenges for implementing the physical layer of high-speed wireline I/Os in CMOS in order to achieve both high data throughput and low power consumption. We will discuss how these goals can be met by proper choice...
