TWEPP 2012 Topical Workshop on Electronics for Particle Physics

Session

A4

ASIC & Packaging

19 Sept 2012, 14:50

Oxford University, UK

Conveners

A4: ASICS and Packaging & Interconnects

• Luciano Musa (CERN)

93. Origami Chip-on-Sensor Design: Progress and New Developments

Mr Christian Irmler (HEPHY Vienna)

19/09/2012, 14:50

Oral

The Belle II SVD will consist of four layers of double-sided silicon detectors, arranged in ladders. Each sensor will be read out individually by utilizing the Origami chip-on-sensor concept, where the APV25 chips are placed on flexible circuits, glued on top of the sensors. Beside a best compromise between low material budget and sufficient SNR, this concept allows efficient CO2 cooling of...

147. Design and characterization of a radiation-tolerant wide dynamic-range DC coupled and double polarity charge-to-digital converter for ionization chambers and diamond detectors

Giuseppe Guido Venturini (Ecole Polytechnique Federale de Lausanne (CH))

19/09/2012, 15:15

Oral

The design is based on charge-to-frequency conversion, with the addition of a new system to reconfigure the front-end - depending on the input signal level to increase the dynamic range at constant sampling frequency. The ASIC has been designed in 0.25 μm radiation tolerant CMOS technology aiming to cover a dynamic range of six decades with a 25kHz sampling rate: design, simulation and...

112. A Radiation-Hard PLL for Frequency Multiplication with Programmable Input Clock and Phase-Selectable Output Signals in 130 nm CMOS

Filip Francis Tavernier (CERN)

19/09/2012, 15:40

Oral

A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320 MHz as a reference and generates clocks at the same frequencies, regardless of the input. Moreover, the outputs are available with a phase resolution of 90° for the 40, 80 and 160 MHz output and 22.5° for the 320 MHz output. The radiation-hard design, integrated in a 130 nm CMOS...