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TWEPP 2012 Topical Workshop on Electronics for Particle Physics

17–21 Sept 2012
Oxford University, UK
Europe/Zurich timezone

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Session

P6

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20 Sept 2012, 14:00
Oxford University, UK

Oxford University, UK

<font face="Verdana" size="2"><b>Clarendon Laboratory</b> Parks Road OX1 3PU, Oxford, United Kingdom

Conveners

P6: Low-power High-Speed CMOS I/Os: Design Challenges and Solutions

  • Mitch Newcomer (University of Pennsylvania)

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  1. 173. Low-power High-Speed CMOS I/Os: Design Challenges and Solutions
    Mr Thomas Toifl (IBM Zurich)
    20/09/2012, 14:00
    Due to the ever-increasing number of transistors on a processor chip, I/Os are more and more becoming the limiting factor on system performance. This presentation will describe the challenges for implementing the physical layer of high-speed wireline I/Os in CMOS in order to achieve both high data throughput and low power consumption. We will discuss how these goals can be met by proper choice...
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