11-15 February 2013
Vienna University of Technology
Europe/Vienna timezone

A 10 MS/s 8-bit Charge-Redistribution ADC for Hybrid Pixel Applications in 65 nm CMOS

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Vienna University of Technology

Vienna University of Technology

Gußhausstraße 25-29, 1040 Wien (Vienna), Austria
Board: 97
Poster Electronics


Tetsuichi Kishishita (University of Bonn)


The design and the measurements of an 8-bit SAR ADC, based on a charge-redistribution DAC, developed for future hybrid pixel applications are presented. This ADC is characterized by superior power efficiency and small area, realized by employing a lateral metal-metal capacitor array and a dynamic 2-stage comparator. To avoid the need for a high-speed clock and its associated power consumption, an asynchronous logic is implemented in a logic control cell. A test chip has been developed in a 65-nm CMOS technology, including eight different flavors of the capacitor layouts, two transimpedance amplifiers for signal inputs, and a custom-made LVDS driver for data transmission. The integral (INL) and differential (DNL) nonlinearities are measured below 0.5 LSB and 0.8 LSB respectively, for the best channel with 10 MS/s. The typical area is 40~$¥mu$m $¥times$ 70~$¥mu$m per channel. The power consumption is estimated as 4~$¥mu$W at 1 MS/s and 38~$¥mu$W at 10 MS/s with a supply rail of 1.2 V. These promising performances based on a natural radiation hardness of transistors due to its thin gate oxide thickness are fascinating for future hybrid detector applications such as a two dimensional readout ASIC for CdTe/CdZnTe detectors with pixel pitch of 200--300~$¥mu$m to realize future hard X-ray space observations, or low-noise and fast readout architecture of the DEPFET and Fine Pixel CCD (FPCCD) as an option of the future ILC(International Linear Collider) vertex detector.
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Primary author

Tetsuichi Kishishita (University of Bonn)

Presentation Materials