The hit information obtained from the sampling ADC system is buffered for the subsequent readout. In parallel a version of this hit information, although reduced in data volume, is provided as trigger primitives with a fixed latency for a digital trigger subsystem. The trigger primitives from up to 18 GANDALF modules contained in a single VME64x/VXS crate are transmitted via the backplane to the so called TIGER module. The synchronous transfer protocol was optimized for low latencies and offers a bandwidth of up to 8 Gbit/s per link. The key components of the TIGER module is a Xilinx Virtex-6 SX315T FPGA, offering vast programmable logic, embedded memory and DSP resources. It is complemented by an additional dual-port double-data-rate memory, a computer-on-module with an Intel Atom processor and a mobile PCI Express graphics processor mezzanine card, respectively. Besides the VXS backplane ports, the board features two optical SFP+ transceivers, 32 LVDS inputs and 32 programmable LVDS outputs and a Gigabit Ethernet port for configuration and monitoring.
The GANDALF module by itself is a 6U-VME64x/VXS carrier board which can host two custom mezzanine cards. Although our initial focus was on the digitization of signals from the recoil detector we tried to keep the module as general as possible. Exchangeable mezzanine cards allow for very different applications such as analog-to-digital (ADC) or time-to digital (TDC) conversion, coincidence matrix formation, fast pattern recognition or fast trigger generation.