Speaker
Description
Summary
CMOS Monolithic Active Pixel Sensors (MAPS) provide an excellent spatial resolution in the order of few micrometer in combination with a low material budget (50 micrometer thickness have been demonstrated) and high radiation hardness. The active volume of the devices is formed by the epitaxial layer of standard CMOS wafers. This allows the integration of pixels together with analogue and digital data processing circuits on-chip.
The MIMOSA-26 MAPS integrates functionalities like pedestal correction, correlated double sampling, discrimination and a data sparsification based on zero suppression combined with a pixel matrix of $2\ \rm cm^2$. The pixel array composed of $576$ lines of $1152$ pixels is read out in a column-parallel rolling-shutter mode. One discriminator per column and the digital data processing circuits are located on the same chip in a $3\ \rm mm$ wide area beneath the pixel matrix allowing for binary hit encoding. This area also contains the circuits for pedestal correction and the configuration memory, which is programmed via JTAG. The preprocessed digital data is read out via two digital $80\ \rm Mbit/s$ data links per sensor, which push their data based on a low-level protocol.
The first CBM Micro Vertex Detector (MVD) prototype based on MIMOSA-26 sensors was recently assembled. To study its tracking performance, it is built as a dual-layer micro-tracking device with four additional sensors arranged in a line as a beam telescope
device. The micro-tracker is sandwiched by two reference stations, again based on the same sensor type, on both sides, respectively. The results demonstrate a detection efficiency above $98.5\%$ and a spatial resolution below $3.8$ micrometer for a high-energy pion beam at the SPS.
In the context of the CBM-MVD prototype project, we developed a scalable and free-running DAQ system which allows to steer and to operate multiple MIMOSA-26 sensors. Both, the sensor control and the data management was carried out by TRBv2 boards developed by the HADES collaboration, which were complemented with general-purpose add-on cards.
Among the functionalities realized in the FPGAs of those boards were data reduction,
quality monitoring, data transportation and slow control of the freely running sensors.
The data was time stamped and transferred via $2\ \rm Gbit/s$ optical links to a local computer. In this setup the total bandwidth of the prototype system was $100\ \rm MB/s$, however the highly scalable implementation allows extending this limit with additional hardware as needed. Furthermore, the modular design of the FPGA firmware supports also newer MIMOSA generations, e.g. MIMOSA-28 as used in the STAR detector and MISTRAL which is currently under development for ALICE.
The beam test at the CERN-SPS validated our design choices and the system could be operated synchronously and dead-time free for several days. A procedure to keep the sensors synchronous even under stress conditions was successfully tested. We introduce the concept of the DAQ system of the CBM-MVD and show beam test results demonstrating the capability of the concept to operate sizable detector systems based on CMOS MAPS. We additionally discuss recent improvements to further increase the system performance.
