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Front-End Electronics for the LHCb Upgrade Scintillating Fibre Tracker

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Beurs van Berlage

Beurs van Berlage

Poster Data-processing: 3a) Front-end Electronics


Herve Chanal (Univ. Blaise Pascal Clermont-Fe. II (FR))


The LHCb detector will be upgraded during the next LHC shutdown in 2018/19. The tracker system will have a major overhaul. Its components will be replaced with new technologies in order to cope with the increased hit occupancy and radiation environment. A detector made of scintillating fibres read out by silicon photomultipliers (SiPM) is studied for this upgrade. Even if this technology has proven to achieve high efficiency and spatial resolution, its integration within a LHC experiment bears new challenges. This detector will consist of 12 planes of 5 to 6 layers of 250μm fibres with an area of $5\times 6$ m$^2$. Its lead to a total of 500k SiPM channels which need to will be read out at 40MHz. This talk gives an overview of the R&D status of the readout board and the PACIFIC chip. The readout board is connected to the SiPM on one side and to the experiment data-acquisition, experimental control system and services on the otherside . The PACIFIC chip is a 128 channel ASIC which can be connected to one 128-channel SiPM without the need for any external component. It includes the analog signal processing and a 2 bits non-linear flash ADC for digitisation. The PACIFIC chip design highlights a very fast shaping (~10ns) and the ability to cope with different SiPM suppliers with a power consumption below 8mW per channel.

Primary author

Herve Chanal (Univ. Blaise Pascal Clermont-Fe. II (FR))


Fred Blanc (Ecole Polytechnique Federale de Lausanne (CH)) Nicolas Geoffroy Pillet (Univ. Blaise Pascal Clermont-Fe. II (FR))

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