22–24 May 2013
TU-Delft
Europe/Zurich timezone
Deadline for booking the Delft channels trip is: Tuesday 7th of May, 2013. More info on "Accommodation & Venue" page

TDC Design and Test Lab (Training Session)

24 May 2013, 14:00
3h
TU-Delft

TU-Delft

Netherlands

Speakers

Mr C. VeerappanDr Francesco Regazzoni

Description

The previous module will be completed by an hands-on laboratory session in which the students will design a small TDC and implement it on the provided FPGA platform. The Xilinx design environment will be utilized for this task, and the resulting configuration file will be tested on an FPGA board.

Presentation materials

There are no materials yet.