Performance benchmark of LHCb code on state-of-the-art x86 architectures

14 Apr 2015, 16:30
15m
B503 (B503)

B503

B503

oral presentation Track8: Performance increase and optimization exploiting hardware features Track 8 Session

Speaker

Rainer Schwemmer (CERN)

Description

For Run 2 of the LHC, LHCb is exchanging a significant part of its event filter farm with new compute nodes. For the evaluation of the best performing solution, we have developed a method to convert our high level trigger application into a stand-alone, bootable benchmark image. With additional instrumentation we turned it into a self-optimising benchmark which explores techniques such as late forking, NUMA balancing and optimal number of threads, i.e. it automatically optimises box-level performance. We have run this procedure on a wide range of Haswell-E CPUs and numerous other architectures from both Intel and AMD, including also the latest Intel micro-blade servers. We present results in terms of performance, power consumption, overheads and relative cost.

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