Prof.
Volker Lindenstruth
(Kirchhoff Institute for Physics)
06/11/2008, 09:00
2. Data Analysis
Plenary
The ALICE High Level Trigger is a high performance computer, setup to process the ALICE on-line data, exceeding 25GB/sec in real time. The most demanding detector for the event reconstruction is the ALICE TPC. The HLT implements different kinds of processing elements, including AMD, Intel processors, FPGAs and GPUs. The FPGAs perform an on the fly cluster reconstruction and the tracks are...
Predrag Buncic
(CERN)
06/11/2008, 09:40
1. Computing Technology
Plenary
CernVM is a Virtual Software Appliance to run physics applications from the LHC experiments at CERN. The virtual appliance provides a complete, portable and easy to install and configure user environment for developing and running LHC data analysis on any end-user computer (laptop, desktop) and on the Grid independently of operating system software and hardware platform (Linux, Windows,...
Mr
Sverre Jarp
(CERN)
06/11/2008, 10:40
1. Computing Technology
Plenary
This talk will start by reminding the audience that Moore's law is very much alive (even after 40+ years of existence).
Transistors will continue to double for every new silicon generation every other year.
Chip designers are therefore trying every possible "trick" for putting the transistors to good use.
The most notable one is to push more parallelism into each CPU: More and longer...
Dr
Ivan Kisel
(Gesellschaft fuer Schwerionenforschung mbH (GSI), Darmstadt, Germany)
06/11/2008, 11:20
2. Data Analysis
Plenary
On-line processing of large data volumes produced in modern HEP experiments requires using maximum capabilities of the computer architecture. One of such powerful feature is a SIMD instruction set, which allows packing several data items in one register and to operate on all of them, thus achieving more operations per clock cycle. The novel Cell processor extends the parallelization further by...
Dr
Anwar Ghuloum
(Intel Corporation)
06/11/2008, 12:00
1. Computing Technology
Power consumption is the ultimate limiter to current and future processor design, leading us to focus on more power efficient architectural features such as multiple cores, more powerful vector units, and use of hardware multi-threading (in place of relatively expensive out-of-order techniques). It is (increasingly) well understood that developers face new challenges with multi-core software...
