28 September 2015 to 2 October 2015
Europe/Zurich timezone

The Phase-1 Upgrade of the ATLAS First Level Calorimeter Trigger

30 Sep 2015, 10:15
Sala 02.1 (Lisbon)

Sala 02.1


IST (Instituto Superior Técnico ) Alameda Campus Av. Rovisco Pais, 1 1049-001 Lisboa Portugal
Oral Trigger Trigger


Reinhard Schwienhorst (Michigan State University (US))


The ATLAS level-1 calorimeter trigger pursues a series of upgrades in order to face the challenges posed by the upcoming increase of the LHC beam energy and luminosity. The hardware built during the Phase-1 upgrade will be installed in 2018. The calorimeter data will be available with a tenfold increase of granularity which allows to employ more sophisticated identification algorithms. To cope with this increase of input data, an entirely new custom electronics processing system will be built exploiting the technological advances in the design of complex PCBs, powerful FPGAs, new crate technologies and high speed optical interconnects.


The level-1 calorimeter trigger (L1Calo) of the ATLAS experiment worked effectively since the start of LHC operations, and has played a major role in the discovery of the Higgs boson. To face the new challenges posed by the upcoming increase of the LHC proton beam energy and luminosity, a series of upgrades is planned. An initial upgrade (Phase-0) is currently in the commissioning phase.
A further, more substantial upgrade (Phase-1) is planned for the LHC shutdown in 2018. The calorimeter trigger identifies electrons, photons, taus and hadronic jets. It also determines total and missing transverse energy and can further analyse the event topology using a dedicated system (L1Topo) incorporating information from both calorimeter and muon triggers. A tenfold increase of the available calorimeter data after the Phase-1 upgrade will allow to replace the currently used sliding window algorithms by more sophisticated identification signatures like shower shapes or jet substructure. This paper presents the newly developed custom electronics for the level-1 calorimeter trigger. The upgrade profits from the recent advances in microelectronics like the design of complex PCBs, powerful FPGAs new crate technologies and high speed optical interconnects.
The calorimeter signals are received via optical fibres and distributed through a custom built optical distribution plant to three distinct processing systems. The signals from the LAr calorimeter come directly from the newly built digital processing system of the LAr calorimeter. The signals from the Tile calorimeter are still processed in the current PreProcessor system. A new rear extension module is designed to distribute the signals electrically to the legacy processing system and optically to the new processing system through the fibre optic plant. Three distinct feature extractor systems are built. They receive the input data in different granularities tailored to employed algorithms. The electron feature extractor (eFEX) receives signals with highest granularity so called supercells which are sums of several calorimeter cells in order to run identification algorithms which calculate shower shape variables. The system consists of 2 ATCA shelves equipped with 12 boards each. Every module processes data from a distinct area in the calorimeter. The jet feature extractor (jFEX) receives data in coarser granularity of 0.1x0.1 in $\eta$x$\phi$ space. It identifies jets and hadronically decaying taus. Furthermore it calculates missing transverse energy. The system consists of 7 boards housed in a single ATCA shelf. The global feature extractor (gFEX) brings all the calorimeter data with a granularity of 0.2x0.2 in $\eta$x$\phi$ space onto a single ATCA board. It is especially designed to identify so called fat jets. Although the three systems are different in the design of the modules, they face common challenges like large numbers of optical input signals, a high density of high speed electrical links on the PCBs and the usage of huge expensive FPGAs.
The presentation reviews the physics impact along with the current status of the hardware design, solutions of various design challenges and the status of early prototypes and demonstrator boards.

Primary author

Reinhard Schwienhorst (Michigan State University (US))


Rainer Stamen (Ruprecht-Karls-Universitaet Heidelberg (DE))

Presentation Materials