TWEPP 2015 - Topical Workshop on Electronics for Particle Physics

28 Sept 2015, 09:00 → 2 Oct 2015, 17:00 Europe/Zurich

Lisbon

Joao Varela (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part), Jorgen Christiansen (CERN)

The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.

LHC experiments (and their operational experience) will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.

Official Web site for local information and registration http://www.lip.pt/events/2015/TWEPP/

The purpose of the workshop is :

- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities

- to review the status of electronics for the LHC experiments

- to identify and encourage common efforts for the development of electronics

- to promote information exchange and collaboration in the relevant engineering and physics communities.

TWEPP-15 is organized with support from:

 

jinst-word-sample_line_numbering.doc

Monday 28 September

12:30 Registration

Opening: 1

Convener: Jorgen Christiansen (CERN)

1 Opening

Speaker: Jorgen Christiansen (CERN)

TWEPP15-Opening.pptx

2 Opening Local Organizer

Speaker: Joao Varela (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)

João Varela.pdf

João Varela.ppt

3 Welcome from Professor Rogério Colaço

4 High-energy physics and associated technologies in Portugal

Portugal joined CERN 30 years ago. This event was coincident with the creation of LIP and the start of activities in Experimental Particle Physics in Portugal. It was also a landmark in the internationalization of Portuguese Science. In this talk we will follow the trajectory of high-energy physics and associated technologies in Portugal with emphasis on the recent projects.

Speaker: Gaspar Barreira (LIP)

Barreira_ID249.pdf

5 Genesis of a Workshop

The LHC Electronics Review Board was created in 1994 to advise the LHC experiments Committee LHCC on rationalization measures in the fields of design, manufacture and operation of electronic systems for LHC experiments. To this end, the LERB found appropriate to launch a series of topical workshops in order to allow for open discussions on the issues at stake. This paper recalls related events and decisions that occurred between 1985 and the approval of the LHC in 1995. The LERB terms of reference and the outcome of the first workshop are presented.

Speaker: Francois Bourgeois (CERN)

genesis_pdf_twepp2015.pdf

16:00 Coffee break

Opening: 2

Convener: Joao Varela (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)

6 ITER Electronics

ITER and future long duration fusion experiments, similarly to other large-scale physics experiments, demand a high degree of automation and high-availability (HA) for the whole plant infrastructure. Highly available systems operate seamlessly in the case of component failure, ensuring safety of equipment, people, environment and investment. Control and Data Acquisition (C&DA) systems for Fusion diagnostics are considered mission-critical and require high degrees of availability. The biggest challenge is providing robust and fault tolerant control systems able to fulfill requirements for RAMI (Reliability, Availability, Maintainability, Inspectability). Also, diagnostics for high performance measurements may be subject to high levels of particles and radiation beyond the existing in previous facilities, and therefore radiation effects in subsystems have to be deeply considered. Use of Commercial Off The Shelf (COTS) components operating under radiation is a reliability concern but, most often there is no alternative to the use of commercial-grade components and the risk associated to their use has to be managed. Mitigationof radiation effects for reliable operation and irradiation testing on a representative environment is of highest relevance for radiation effects studies in emerging technologies.

Speaker: Bruno Goncalves (IPFN/IST)

BGoncalves_ID244.pdf

BGoncalves_ID244.pptx

7 High-Performance Analog-to-Digital Converters - Evolution and Trends

The Analog-to-Digital Converter (ADC) is a fundamental building block of many systems. We will address the trends and evolution of performance observed in ADC design over the last decade. Some of the solutions recently published in the literature, to improve energy efficiency and address the limitations found in advanced CMOS processes, will be discussed. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

Speaker: Pedro Figueiredo (Synopsys Lisbon)

Pedro_Figueiredo.pdf

Pedro_Figueiredo.pptx

18:30 Welcome Reception

Tuesday 29 September

Invited Plenary

Convener: Jorgen Christiansen (CERN)

8 Status and Future Prospects of High Time Resolution Photon Counting Sensor Arrays

Photon counting at a very large scale has recently become available, thanks to the introduction of CMOS single-photon avalanche diodes and analog/digital silicon photomultipliers. With the continuous technological push demanded by Moore’s Law and the introduction of 3D integration, achieving ever increasing fill factors and near-picosecond timing resolutions with integrated time-to-digital conversion are becoming realistic goals in the near term. In this talk, I will review current and future photon counting sensors, looking at trade-offs and trends in the context of these technological advances, focusing at emerging applications and at the challenges they will bring.

Speaker: Edoardo Charbon (TU Delft)

Charbon_ID237.pdf

Production, testing and reliability

Convener: Ken Wyllie (CERN)

9 ATLAS Pixel Detector ROD card from IBL towards Layers 2 and 1

ATLAS Experiment has reworked and upgraded some systems during the 2014-2015 LHC shut down and the Pixel Detector has inserted an additional layer: the Insertable B-Layer. The Readout-Driver card, the Back-of-Crate card, and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. Recent collaboration efforts focused on hardware and firmware and now the work is moving towards the DAQ upgrades of the Layers 2 and 1, leaving the sensors untouched. Time plan is to approach a complete DAQ hardware-software installation by the end of 2015.

Speaker: Alessandro Gabrielli (Universita e INFN, Bologna (IT))

ATLAS Pixel Detector ROD card from IBL towards Layers 2 and 1 .pdf

Programmable Logic, design tools and methods

Convener: Jose Carlos Rasteiro Da Silva (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)

10 Implementation of the Timepix chip in the Scalable Readout System

As proof of principle for a Pixel-TPC, the Timepix ASIC featuring a matrix of 256 x 256 charge sensitive pixels was chosen as anode readout of a gaseous detector. To read out more than a few chips, a new readout system was designed by developing dedicated hardware and FPGA firmware, on which the presentation will focus. The Scalable Readout System, as a general system also used for example in LHC experiments, was used for the implementation. In a test beam, 160 chips with about 10 mio. channels were read out in parallel - a new record for a TPC.

Speaker: Michael Lupberger (University of Bonn)

MLupberger_ID98.pdf

11 A Novel Approach for Pulse Width Measurements in an FPGA

High precision time measurements are a crucial element in particle identification experiments, which likewise require pulse width information for charge and Time-over-Threshold (ToT) measurements. In almost all of the FPGA-based TDC applications, pulse width measurements are implemented using two of the TDC channels for leading and trailing edge time measurements individually. This method however, requires double the number of resources and therefore this paper presents a novel way of measuring pulse width using a single TDC channel, while still achieving high precision (as low as 12ps RMS).

Speaker: Cahit Ugur (GSI - Helmholtzzentrum fur Schwerionenforschung GmbH (DE))

Ugur_ID186.pdf

Power, Grounding and Shielding

Convener: Ken Wyllie (CERN)

12 EMC Studies for the Vertex Detector of the Belle II Experiment

The upgrade of Belle II experiment plans to use a vertex detector based on two different technologies. DEPFET pixel (PXD) technology and doubleside silicon microstrip (SVD) technology. The vertex electronics are characterized by the topology of SVD bias that forces to design a complex grounding and the complex topology of the PXD power cable bundle that may introduce some noise inside vertex area. This paper presents a general overview of the EMC issues present in the vertex system, based on EMC test on SVD prototype and a study of noise propagation in the PXD cable bundle based on MTL theory.

Speaker: Richard Thalmeier (Austrian Academy of Sciences (AT))

2015-09-29_Slides_TWEPP_Richard_Thalmeier.pdf

10:40 Coffee break

10:55 Group Photo

Programmable Logic, design tools and methods

Convener: Magnus Hansen (CERN)

13 A framework for porting the NeuroBayes machine learning algorithm to FPGAs

The NeuroBayes machine learning algorithm is deployed for online data reduction at the pixel detector of Belle-II. In order to test, characterize and easily adapt its implementation on FPGAs, a framework was developed. Within the framework a HDL model, written in python using MyHDL, is used for fast exploration of possible configurations. Under usage of input data from physics simulations figures of merit like throughput, accuracy and resource demand of the implementation are evaluated in a fast and flexible way. Functional validation is supported by usage of unit tests and HDL simulation for chosen configurations.

Speaker: Steffen Baehr (Karlsruhe Institute of Technology)

twepp_2015_sb_v6.pdf

Radiation tolerant components and systems

Convener: Prof. Lutz Feld (RWTH Aachen University)

14 A radiation tolerant Data link board for the ATLAS TileCal upgrade

We describe the latest (last?) full functionality revision of the high-speed data link board for the ATLAS TileCal phase 2 upgrade. It is highly redundant, using two Kintex-7 FPGAs and two Molex QSFP+ electro-optic modules. The FPGAs are remotely configured through two radiation-hard CERN GBTx deserialisers (GBTx), which also provide the LHC-synchronous system clock. The four QSFP+ uplinks transmit data at 10 Gbps. Virtually all single-point error modes are removed, and a combination of triple-mode redundancy, internal and external scrubbing will adequately protect against radiation-induced errors.

Speaker: Christian Bohm (Stockholm University (SE))

ATL-TILE-TWEPP-15.pdf

15 Development of ATLAS Liquid Argon Calorimeter Read-out Electronics for the HL-LHC

The high-luminosity phase of the Large Hadron Collider will provide a 5-7 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon Calorimeters and their read-out system. An improved trigger system with higher acceptance rate and longer latency and a better radiation tolerance require an upgrade of the read-out electronics. Concepts for the future read-out of the 183.000 calorimeter channels at 40-80 MHz and 16 bit dynamic range, and the development of radiation tolerant, low noise, low power and high-bandwidth electronic components will be presented.

Speaker: Mitchell Franck Newcomer (University of Pennsylvania (US))

ATL-LARG-SLIDE-2015-735.2.pdf

ATL-LARG-SLIDE-2015-735.2.pptx

16 Radiation tolerance of the readout chip for the Phase I upgrade of the CMS pixel detector

For the Phase I upgrade of the CMS pixel detector a new digital readout chip (ROC) has been developed. An important part of the design verification are irradiation studies to ensure sufficient radiation tolerance. The presentation summarizes results of the irradiation study on the final ROC design for the detector layers 2 - 4. Samples have been irradiated with 23 MeV protons to accumulate the expected lifetime dose of up to 1.2 MGy. Additionally, very high doses of up to 4.2 MGy have been tested to explore the capabilities of the current chip design on 250 nm CMOS technology.

Speaker: Jan Hendrik Hoss (Eidgenoessische Tech. Hochschule Zuerich (CH))

2015_09_28_TWEPP.pdf

Packaging and interconnects

Convener: Magnus Hansen (CERN)

17 Construction and Test of the First Belle II SVD Ladder Implementing the Origami Chip-on-Sensor Design

The Belle II Silicon Vertex Detector consists of four layers of double-sided silicon detectors (DSSDs), composed of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits, which are glued on the top of the sensors. This concept allows for low material budget and efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements, cooling and beam tests.

Speaker: Mr Christian Irmler (Austrian Academy of Sciences (AT))

2015.09.29_twepp2015_irmler.pdf

2015.09.29_twepp2015_irmler.pptx

Trigger

Convener: Magnus Hansen (CERN)

18 Alice CTP upgrade

The ALICE Central Trigger Processor (CTP) has been upgraded for LHC Run 2, amongst other motivations in order to improve the data-taking efficiency for the Transition Radiation Detector (TRD). There is also a new CTP interaction record with a new DDL link , a 2 GB SODIMM DDR3 memory, an extension of the number of clusters and an extension of functionality for classes. The CTP switch has been incorporated directly onto the new LM0 board. A design proposal for an ALICE CTP upgrade for LHC Run 3 will also be presented. A part of development is a low latency high bandwidth interface in order to minimize an overall trigger latency

Speaker: Jan Pospisil (Acad. of Sciences of the Czech Rep. (CZ))

TWEPP-15_v7.pdf

TWEPP-15_v7.pptx

12:25 Lunch

Invited Plenary

Convener: Philippe Farthouat (CERN)

19 Past and future microelectronics in HEP

Moore’s law celebrates this year its 50th anniversary. The technologies developed following its paradigm have brought profound changes in the way we work and communicate in our everyday life. The massive introduction of microelectronics in the design of experiments and detectors for High Energy Physics at LHC has also changed the way we conceive, design and operate experiments. Despite the innumerable threats of imminent saturation of its capabilities, microelectronics has continued to allow higher levels of integration at a lower cost per transistor, following the original Moore’s curve. New HEP experiments and upgrades for the 2020’s can now be planned with much more ambitious plans where perhaps the only limits will derive from our imagination and from our ability in managing complex projects and their risks, rather than from any intrinsic technological limitation.

Speaker: Alessandro Marchioro (CERN)

Marchioro.pdf

Marchioro.pptx

Trigger

Convener: Stefano Veneziano (Universita e INFN, Roma I (IT))

20 Trigger Algorithms and electronics for the ATLAS Muon NSW Upgrade

The ATLAS New Small Wheel (NSW), comprising MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), will upgrade the ATLAS muon system for a high background environment. Particularly, the NSW trigger will reduce the rate of fake triggers coming from background tracks in the endcap. We will present an overview of the NSW trigger processor, the sTGC and MM trigger algorithms, and the hardware implementation - an ATCA system with FPGA-based trigger processors. Finally, we will detail the challenges of meeting the low latency requirements of the trigger system and coping with the high background rates of the HL-LHC.

Speaker: Liang Guan (University of Michigan)

ATLAS_NSW_Trigger_LiangGuan_TWEPP_vf.pdf

21 Operation of the upgraded ATLAS Level-1 Central Trigger System

The ATLAS Level-1 Central Trigger system is responsible for forming the level-1 trigger decision based on the information from the calorimeter and muon trigger processors. It has undergone a major upgrade of its key components to cope with the increase of luminosity and physics cross-sections in Run 2. In this presentation, we give an overview of the commissioning and the overall performance of this upgraded system with the first LHC beams. We also discuss all challenges which had to be overcome to provide a reliable, robust and flexible system in time for the first collisions.

Speaker: Antoine Marzin (CERN)

CTP_twepp2015.pdf

22 Design of a Hardware Track Finder (Fast Tracker) for the ATLAS Trigger

The ATLAS Fast TracKer (FTK) is a custom electronics system that will operate at the full Level-1 accept rate, 100 kHz, to provide high quality tracks as input to the High-Level Trigger. The event reconstruction is performed in hardware, thanks to the massive parallelism of associative memories (AM) and FPGAs. We present the advantages for the physics goals of the ATLAS experiment and the recent results on the design, technological advancements and testing of some of the core components used in the processor.

Speaker: Viviana Cavaliere (Univ. Illinois at Urbana-Champaign (US))

FTkTWEPP2015_2.pdf

ASICs

Convener: Christophe De La Taille (OMEGA (FR))

23 A High Frame Rate Pixel Chip Design for Synchrotron Radiation Applications

A hybrid pixel detector working in the single photon counting mode was designed for the High Energy Photon Source (HEPS) in China. The pixel readout chip contains an array of 104 × 72 pixels with a pixel size of 150µm×150µm, each with a counting depth of 20bit. The measurement showed 118e- equivalent noise after bump bonding and non-uniformity less than 55e- after threshold equalization. All functionalities were proved to be normal at a frame rate of 1.2kHz with a dead-time less than 175ns/frame, which are greatly improved compared with the existing pixel system.

Speaker: Wei Wei (IHEP, CAS, China)

A High Frame Rate Pixel Chip Design for Synchrotron Radiation Applications.ppt

24 65 nm CMOS analog front-end for pixel detectors at the HL-LHC

This work is concerned with the design and the experimental characterization of analog front-end electronics conceived for experiments with unprecedented particle rates and radiation levels at future high-energy physics colliders. A prototype chip integrating different test structures has been submitted in the framework of the CHIPIX65 project. These structures are standalone channels for the readout of hybrid pixels, featuring a charge sensitive preamplifier as the first stage of the readout chain, a high-speed comparator and a circuit for fine threshold tuning. The full characterization of the analog front-end will be discussed in the conference paper.

Speaker: Luigi Gaioni (University of Bergamo)

twepp2015_gaioni.pdf

twepp2015_gaioni.ppt

25 Front End ASIC for AGIPD, a high dynamic range fast detector for the European XFEL

Adaptive Gain Integrating Pixel Detector (AGIPD) is a hybrid pixel X-ray detector for the European-XFEL. The detector's important part is the radiation tolerant front end ASIC fulfilling the European-XFEL requirements: High dynamic range - from sensitivity to single 12.5keV-photons up to 10⁴ photons. It is implemented using the dynamic gain switching technique with three possible gains of the charge sensitive preamplifier. Each pixel can store up to 352 images in memory operated in random-access mode at ≥4.5 MHz frame rate. An external vetoing may be applied to overwrite “bad” frames.

Speaker: Dr Alexander Klyuev (Deutsches Elektronen-Synchrotron)

klyuev_twepp2015_v_0.6_part1.pdf

klyuev_twepp2015_v_0.6_part2.pptx

16:05 Coffee break

Poster: Session 1

Conveners: Ken Wyllie (CERN), Mitchell Franck Newcomer (University of Pennsylvania (US))

26 TopMetal2-: a direct charge-collecting sensor for high energy physics and imaging in XFAB 350nm process

This work presents the design and characterization of TopMetal2- chip, a direct charge-collecting sensor via 25x25um2 top metal placed on the top of each pixel. The TopMetal2- chip has been manufactured in the XFAB 350nm CMOS Imaging Sensor process. The TopMetal2- features 72x72 pixel array of 83.2um pixel pitch. Post-layout simulations and test results show the gain of charge sensitive amplifier (CSA) with 5fF feedback capacitor is 320mV/fC. The estimated equivalent noise charge (ENC) of the readout system is 30e- rms at 5us peaking time with a detector capacitance of 23fF.

Speaker: Mr Chaosong Gao (Central China Normal University CCNU (CN))

topmetal_II- a direct charge sensro for high energy physics and imaging applications.pdf

27 GEMMA and GEMINI, two dedicated mixed-signal ASICs for Triple-GEM detectors readout

GEMMA and GEMINI, two integrated frontends for the Triple-GEM detector are presented. The ASICs aim to improve detector readout performance in terms of count rate, adaptability, portability and power consumption. GEMMA target is to embed counting, timing and spectroscopic measurements in a single 8-channel device, managing a detector capacitance up to 15pF. GEMINI is dedicated to counting measurements, embedding 16 channels with a detector capacitance up to 40pF. Both prototypes, fabricated in 130nm and 180nm CMOS respectively, feature an automatic on-chip calibration circuit, compensating for process/temperature variations.

Speaker: Alessandro Pezzotta (University of Milano-Bicocca)

posterTWEPP.pdf

28 Design of a 10-bit segmented current-steering Digital-to-Analog Converter in CMOS 65nm technology for the bias of new generation readout chips in high radiation environment

A new pixel front end chip for HL-LHC experiments in CMOS 65nm technology is under development by the CERN RD53 collaboration together with the Chipix65 INFN project. This work describes the design of a 10-bit segmented current-steering Digital-to-Analog Converter (DAC) to provide a programmable bias current to the analog blocks of the circuit. The main requirements are monotonicity, good linearity, limited area consumption and radiation hardness up to 10 MGy. The DAC was prototyped and electrically tested, while irradiation tests are foreseen for summer 2015. The implementation and test results will be shown.

Speaker: Flavio Loddo (INFN-BARI)

Loddo_ID18.pdf

29 TOFPETv2: a high-performance ASIC for time and amplitude measurements of SiPM signals in time-of-flight applications

We present the design and simulation of a readout and digitization ASIC for radiation detectors using Silicon Photomultipliers. The circuit, designed in standard CMOS 110 nm technology, has 64 independent channels optimized for time-of-flight measurement in PET or other applications. The chip has quad-buffered TDCs and charge integration ADCs in each channel with linear response in the range 0-1500 pC and 600 kHz maximum event rate per channel. Simulation results show that for an impulse charge of 200fC the circuit has 25 dB SNR, 93 ps r.m.s. time resolution, and 5 mW power consumption.

Speaker: Agostino Di Francesco (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)

30 A 12bits 40MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout

We present a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy allows also a digital background calibration, based on a code density analysis, to compensate the capacitors mismatching effects. The total of capacitors used in this architecture is limited to a half of the one in a classical SAR design. Only 211 unit capacitors were necessary to reach 12bit resolution, and the switching algorithm is intrinsically monotonic. The design is fully differential featuring 12-bit 40MS/s in a CMOS 130nm 1P8M process.

Speaker: mohamed zeloufi (LPSC)

poster_TWEPP2015_zeloufi-4.pdf

31 Ongoing studies for the control system of a serially powered ATLAS pixel detector at the HL-LHC

In terms of the Phase-2 Upgrade of the ATLAS detector, the entire inner tracker (ITK) of ATLAS will be replaced. This includes the pixel detector and the corresponding detector control system (DCS). The current baseline is a serial powering scheme of the detector modules. Therefore a new detector control system for ATLAS pixel is being developed with emphasis on the supervision of serially powered modules and radiation tolerance. The concept of the DCS for ATLAS pixel after the Phase-2 upgrade is presented, as well as the status of development including tests with the prototype ASIC.

Speaker: Susanne Kersten (Bergische Universitaet Wuppertal (DE))

TWEPP_2015_posterA0-V5.pdf

32 Characterization of a Three-Side Abutable Cmos Pixel Sensor with Digital Pixel and Data Compression for Charged Particle Tracking : PIXAM

CMOS pixel sensor technology has been chosen to equip the new trackers in ALICE foreseen for HL-LHC. PIXAM is the final prototype from a R&D program specific to the Muon Forward Tracker which intends to push significantly forward the performances of the mature rolling shutter (RS) architecture. By implementing a digital pixel in addition with group of rows for the readout operation, the PIXAM sensor increases the RS readout speed while keeping constant the power consumption. This paper will describe shortly the ASIC architecture and will focus on the sensor analogue and digital performances obtained in laboratory.

Speaker: Fabrice Guilloux (CEA/IRFU - Centre de Saclay (FR))

PosterTwepp2015_v6.pdf

33 QIE12: A New High-Performance ASIC For the ATLAS TileCal Upgrade

We present results on the QIE12, a custom ASIC, being developed for the ATLAS TileCal Phase 2 Upgrade. The design features 1.5 fC sensitivity, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution.  It has a programmable shunt output for monitoring the integrated current. The device operates with no dead-time at 40 MHz, making it ideal for calorimetry at the LHC. We present bench measurements and integration studies that characterize the performance, radiation tolerance measurements, and the design for the ATLAS TileCal detector for the Phase 2 Upgrade.

Speaker: Gary Drake (Argonne National Laboratory (US))

150921_twepp_drake_qie_poster_final.pdf

34 A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS Driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip.

This work presents two essential components for the high speed data transmission of the ALICE inner detector front-end chip. The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz clock for the 1.2 Gb/s Double Data Rate serializer and a 200 MHz output for the 400 Mb/s driver. The pseudo-LVDS driver transmits the data from the pixel chip with a limited number of signal lines. It drives a 5m-6.5m differential transmission line by steering a maximum 5mA at the targeting speeds of 1.2Gb/s. A pre-emphasis technique was adopted to overcome the cables RC limitations. Both circuits are designed in the same CMOS 0.18 μm technology used for the pixel chip.

Speaker: Alessandra Lattuca (Universita e INFN Torino (IT))

POSTER_TWEPP.pdf

35 Performance of the new Amplifier-Shaper-Discriminator chip for the ATLAS MDT Chambers at the HL-LHC

The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for MDT drift tubes. The first processing stage, the channel Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 * 2.9 mm2 size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.

Speaker: Robert Richter (Max-Planck-Institut fuer Physik (Werner-Heisenberg-Institut) (D)

TWEPP15_ASD4_R_Richter_vs3.pdf

TWEPP15_ASD4_R_Richter_vs3.ppt

36 Design of the NSW Read Out Controller ASIC

Part of the New Small Wheel ATLAS Phase-1 Upgrade, the Read Out Controller ASIC will aggregate, process and format the data generated by the VMM front-end chips. The ASIC has a flexible architecture designed to optimize the data bandwidth usage for Micromegas and sTGC detectors and for different NSW regions with different hit rates. The ROC will concentrate the Level-0 data streams from up to 8 VMMs, will filter the data based on the Level-1 BCID and transmit the data to FELIX using up to four GBT E-Links, each capable of 320 Mbps data transmission.

Speaker: Radu Mihai Coliban

Poster_TWEPP_ROC_v5.pdf

37 A time-based front-end ASIC for the Silicon micro-strip sensors of the PANDA Micro Vertex Detector

Among the many detectors planned for the PANDA experiment that will take place at the future FAIR accelerator facility, the innermost is the Micro Vertex Detector (MVD). This detector foresees both pixel and strip silicon sensors. The readout chip for the strip sensors of the MVD, named PASTA (PAnda STrip Asic), was developed according to a time-based architecture aiming at Time over Threshold measurements through a high resolution Time to Digital Converter (TDC). A basic overview of the functionalities and a description of the main blocks of the PASTA chip will be presented. Supported by BMBF, HIC4FAIR and JCHP.

Speaker: Mr Valentino Di Pietro (II. Physikalisches Institut, JLU Gießen)

TWEPP2015_Poster.pdf

38 Trigger and readout electronics for the STEREO experiment.

The STEREO experiment will search for a sterile neutrino by measuring the anti-neutrino energy spectrum as a function of the distance from the source, the ILL nuclear reactor. A dedicated electronic, hosted in a single µTCA crate, was designed for this experiment. It performs triggering in two stages with various selectable conditions, processing and readout via UDP/IPBUS on 68 photomultiplier signals continuously digitized at 250 MSPS. Additionally, for detector performance monitoring, the electronics allow online calibration by driving LED synchronously with the data acquisition. This paper will describe the electronics requirements, architecture and the performances achieved.

Speaker: Olivier Raymond Bourrion (Centre National de la Recherche Scientifique (FR))

stereoDAQ_twepp_2015.pdf

39 Readout and data acquisition in the NEW detector based on SRS-ATCA

The Scalable Readout System (SRS) was defined by the CERN RD51 Collaboration as an scalable readout platform for a wide range of front ends. In 2014, SRS was ported to the ATCA (Advanced Telecommunications Computing Architecture) standard. NEXT is an underground experiment aimed at searching for neutrinoless double-beta decay. NEXT-DEMO, a small-scale demonstrator, was read-out using SRS. NEXT has adopted SRS-ATCA for its first stage, called NEW. Our presentation will describe the readout, DAQ and trigger for NEW based on SRS-ATCA. This is, to our knowledge, the first experiment operating entirely on SRS-ATCA.

Speaker: Dr Raul Esteve (Universitat Politècnica de València)

Poster_TWEPP2015_v3.pdf

40 The NA62 Liquid Krypton calorimeter readout system.

The NA62 experiment at CERN SPS accelerator will study the ultra-rare decays of charged kaons. The high-resolution Liquid Krypton (LKr) electromagnetic calorimeter is a key component of the experiment photon-veto system. The new LKr readout system comprises 14 thousand 14-bit ADC acquisition channels, 432×1 Gbit Ethernet data request and readout links routed by 28×10 Gbit network switches to the experiment computer farm, and distinct timing, trigger and control (TTC) distribution system. This paper presents the architecture of the LKr readout and TTC systems, the overall performance and the first successfully collected experiment physics data.

Speaker: Vladimir Ryjov (CERN)

CREAM_TWEPP_2015_Poster_A0_v3.pdf

41 The Giga Bit Transceiver based Expandable Front-End (GEFE) - a new radiation tolerant acquisition system for beam instrumentation

The Giga Bit Transceiver based Expandable Front-End (GEFE) is a multipurpose FPGA-based radiation tolerant card. It is foreseen to be the new standard FMC carrier for digital front-end applications in the CERN BE-BI group. Its intended use ranges from fast data acquisition systems to slow control installed close to the beamlines, in a radioactive environment exposed to total ionizing doses of up to 600 Gy. This paper introduces the architecture of the GEFE, its features as well as examples of its application in different setups.

Speaker: Manoel Barros Marin (CERN)

gefe_twepp2015_poster.pdf

42 Multi-Gigabit Wireless Data Transfer using the Millimeter Wave Band at 60 GHz

Wireless techniques have developed extremely fast the last decade, and using them for data transfer in particle phyics detectors is not science fiction any more. In this paper we describe the status of the first prototype of the 60 GHz wireless Multi-Gigabit data transfer topology current under development at University of Heidelberg using IBM 130 nm SiGe HBT technology. The wireless transceiver consist of a transmitter and receiver. The 60 GHz band is very suitable for high data rate and short distance applications as for example needed in the HEP experiments and other detector facilities.

Speaker: Hans Kristian Soltveit (University of Heidelberg)

43 Development of a Standardized Readout System for Active Pixel Sensors in HV/HR-CMOS Technologies for ATLAS Inner Detector Upgrades

The LHC Phase-II Upgrade results in new challenges for tracking detectors in terms of cost effectiveness, resolution, etc. Active Pixel Sensors in HV/HR - CMOS technologies show promising results coping with these challenges. In order to demonstrate the feasibility of the hybrid modules of active CMOS sensor and readout chip for the future ATLAS Inner Tracker, an ATLAS R&D project has started. After introducing the basic concepts and the demonstrator program, the development of an ATLAS compatible readout system will be presented as well as tuning procedures and measurements with demonstrator modules to test the system.

Speaker: Julia Katharina Rieger (Georg-August-Universitaet Goettingen (DE))

Rieger_TWEPP_2015.pdf

44 Front-End electronics for the FAZIA project

FAZIA is a multidetector specifically designed to optimize ion identification in heavy-ion experiments. This multidetector is modular and it is based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI scintillator associated to a photodiode. Its electronic is fully digital. The objective to push at maximum the ion identification capability while preserving excellent energy resolution, will be reached also using pulse shape analysis techniques and making an intensive use of high-speed flash ADCs. This paper presents the front-end part of this electronics.

Speaker: Franck SALOMON (Institut de Physique Nucléaire d'Orsay)

Salomon_ID50.pdf

45 The SST-1m prototype camera for the Cherenkov Telescope Array

A prototype camera for the single mirror Small Size Telescope (SST-1m) of the Cherenkov Telescope Array has been designed and is under construction. The camera is a hexagonal matrix of 1296 large area (95 mm^2) hexagonal silicon photomultipliers. The fully digital readout and trigger system, DigiCam, allows for high data transfer rates in an extremely compact design. The camera will be installed on a 4m dish diameter telescope prototype in summer 2015. In this presentation, the status of the project will be reported.

Speaker: Enrico Junior Schioppa (Universite de Geneve (CH))

Schioppa_TWEPP2015_CTA_SST-1M_camera_whiteVersion.pdf

46 Performance of the sROD demonstrator for the ATLAS Tile Calorimeter Phase II Upgrade

The super Read Out Driver (sROD) demonstrator is a high performance double AMC board based on FPGA resources and QSFP modules. This board has been designed in the framework of the ATLAS Tile Calorimeter (TileCal) Demonstrator Project for the Phase II Upgrade as the first stage of the off-detector electronics. The sROD demonstrator has been conceived for receiving and processing the data coming from the on-detector electronics of the TileCal Demonstrator module, as well as for configuring it. Moreover, the sROD demonstrator handles the communication with the Detector Control System to monitor and control the on-detector electronics.

Speaker: Fernando Carrio Argos (Instituto de Fisica Corpuscular (ES))

TWEPP2015_FCarrio.pdf

47 The Clock and Control System for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade

A Liquid-argon Trigger Digitizer Board (LTDB) is being developed to demonstrate the functionality of the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics upgrade. The LTDB located at the front end needs to obtain the clock signals and be configured and monitored remotely from the back end. A clock and control system, which uses ASICs including GBTX and GBT SCA at the front end, commercial components at the back end, and optical links between the front end and the back end, is being developed. The design and evaluation of the clock and control system are presented in this paper.

Speaker: Tiankuan Liu (Southern Methodist University)

Poster control link.pdf

48 Self-Triggering Readout System for the Neutron Lifetime Experiment PENeLOPE

PENeLOPE is an a neutron lifetime measurement experiment at the Forschungsreaktor Muenchen II aiming to improve a precision of the measurement by one order of magnitude. The experiment employes state-of-the-art readout electronics and high performance data acquisition system. The system features a continuos noise measurement and pedestal tracking, programmable threshold, high voltage control, cryogenic enviroment and the novel Switched Enabeling Protocol (SEP) developed for passive splitted optical networks. The SEP is a transport level protocol providing access to muplitple slaves connected to a star-topology optical network on a time-division multiplexing maner.

Speaker: Mr Dominic Gaisbauer (TU München Physikdepartment E18)

twepp2015.pdf

49 New Fast Beam Conditions Monitoring (BCM1F) system for CMS.

The CMS Beam Radiation Instrumentation and Luminosity (BRIL) project is composed of several systems providing the experiment protection from adverse beam conditions, measuring the online luminosity and beam background. Although the readout bandwidth of the Fast Beam Conditions Monitoring system (BCM1F), was sufficient for the initial LHC conditions, the foreseen enhancement of the beams parameters after the LHC Long Shutdown-1 (LS1) imposed the upgrade of the system. This paper presents the new BCM1F, which is designed to provide real-time fast diagnosis of beam conditions and instantaneous luminosity with readout able to resolve the 25 ns sub-bunch structure.

Speaker: Ms Agnieszka Zagozdzinska (CERN/WUT)

Poster_PWEPP2015_v5.pdf

50 The CMS Beam Halo Monitor Electronics

The CMS Beam Halo Monitor was installed during LHC LS1 to measure the machine induced background for Run II. The system is composed of Cherenkov radiators coupled to photomultipliers. The readout electronics uses new components developed for the CMS HCAL, adapted to beam monitoring requirements. The signal is digitized by a charge integrating ASIC (QIE10), which also provides timing with ns resolution. The backend electronics uses microTCA; it receives data via 5 Gbps optical links and records occupancy histograms. The electronics has been operational since the first beams of Run II and has served as a demonstration of new technologies.

Speaker: Nicolo Tosi (Universita e INFN, Bologna (IT))

PosterTWEPP.pdf

51 The New Front-End Electronics For the ATLAS Tile Calorimeter Phase 2 Upgrade

The Tile Calorimeter (TileCal) is the main hadronic calorimeter of the ATLAS experiment. TileCal will undergo a major replacement of its readout electronics for the upgrade of the LHC in 2024. The calorimeter signals will be digitized and sent directly to the off-detector electronics, where the signals are reconstructed and shipped to the first level of trigger at a rate of 40 MHz. Three different options are presently being investigated for the front-end electronic upgrade. One hybrid demonstrator prototype module with the new calorimeter module electronics, but still compatible with the present system, has been built.

Speaker: Agostinho Da Silva Gomes (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)

twepp2015newTileFE-4.pdf

52 A Signal Distribution Board for the Timing and Fast Control Master of the CBM Experiment

For the CBM experiment a Timing and Fast-Control (TFC) system is being developed. In the detector readout, FPGA-based data processing boards (DPB) are organized in a large number of computing crates. At the crate level, the TFC master is connected to one TFC slave per crate, whereas the DPB AMCs are interconnected by the crates’ infrastructure. In this article, an FMC-based signal distribution board is proposed allowing the transmission of a high-quality clock and timing and fast-control data from and to connected TFC slaves at distances of about 30 meters using twisted-pair cables.

Speaker: Lukas Meder (Karlsruhe Institute of Technology)

Meder_KIT_TFC_IF_Board_Twepp15.pdf

53 Commissioning of the Upgraded CSC Endcap Muon Port Cards at CMS

We report on the status of commissioning of the upgraded Muon Port Cards in the Level 1 Trigger electronic system serving the Endcap Cathode Strip Chamber (CSC) sub-detector at the CMS experiment at CERN. After presenting an overview of the existing system and upgrade requirements, we describe the new Muon Port Card FPGA mezzanine and its firmware developed to drive the new 3.2Gbps optical links. Results of initial tests with the existing and upgraded CSC Track Finder boards and further plans are given in the concluding sections.

Speaker: Mr Mikhail Matveev (Rice University)

54 The Level-0 Trigger Processor for the NA62 experiment

In the NA62 experiment at CERN-SPS, the communication between detectors and the Lowest Level (L0) trigger processor is performed via ethernet packets, using the UDP protocol. The L0 trigger processor handles the signals from sub-detectors that take part to the trigger generation and, in order to chose the best solution, two different approaches have been implemented. The first approach is fully based on an FPGA device while the second one joins an off-the-shelf PC to the FPGA.
 The performance of the two systems will be discussed and compared.

Speaker: Dario Soldi (Universita e INFN Torino (IT))

POSTER_Soldi_TWEPP2015_final2.pdf

55 Test of a demonstrator of an MDT-based first level muon trigger for HL-LHC under realistic operating conditions.

Selective triggers are essential for the programme of the ATLAS experiment at the HL-LHC. Its first level muon trigger rate is dominated by low momentum muons, selected due to the moderate resolution of the trigger chambers. This limitation can be overcome by including the precision muon drift tube (MDT) chamber data. This requires a fast MDT read-out and fast track reconstruction. A demonstrator of this read-out with an FPGA was successfully tested under realistic conditions at the GIF. The data could be reconstructed with a fast algorithm on an ARM CPU within the first level trigger latency.

Speaker: Hubert Kroha (Max-Planck-Institut fuer Physik (Werner-Heisenberg-Institut) (D)

twepp2015_poster_MDTtrigger.pdf

56 A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade

The increase of luminosity at the High Luminosity Large Hadron Collider (HL-LHC) will require the main experiments to use the tracker information at Level-1 trigger system in order to maintain an acceptable trigger rate. To extract the track information at the required latency – few microseconds - a dedicated hardware has to be used. We present the tests of a prototype system based on pattern recognition mezzanine as core of pattern recognition and track fitting for HL-LHC ATLAS and CMS experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.

Speaker: Giacomo Fedi (Universita di Pisa & INFN (IT))

57 A High Bandwidth and versatile Advanced MC Board

We developed a new AMC board based on AMC.0, named as Trigger Receiver Board (TRB). TRB is a high bandwidth data-stream processor, using one Xilinx Artix-7 FPGA. This FPGA has 16 MGTs running up to 6.4Gbps, making TRB capable to handle total bandwidth up to 100 Gbps. Also there are LVDS I/Os routed to a FMC connector for commercial extend board and two micro connectors for MicroZED. One on-board 4Gb DDR3 chip running at 800MT/s is the main memory of microblaze-based embedded system, as well as the data buffer of logical part

Speaker: Jianmeng Dong (Universite Libre de Bruxelles (BE))

A High Bandwidth and versatile Advanced MC Board

58 Algorithm and implementation of muon trigger and data transmission system for barrel-endcap overlap region of the CMS detector

The CMS experiment is currently undergoing upgrade of its trigger, including the Level-1 muon trigger. In the barrel-endcap transition region it is necessary to merge data from 3 types of detectors - RPC, DT and CSC. The Overlap Muon Track Finder (OMTF) uses the novelty approach to concentrate and process those data in an uniform manner. The paper presents the algorithm and FPGA firmware implementation of the OMTF and its data transmission system in CMS. The OMTF is subject to significant changes during optimizations based on physical simulations. Therefore a special, high level, parametrized HDL implementation is necessary.

Speaker: Dr Wojciech Zabolotny (University of Warsaw (PL))

plakat_OMTF.pdf

59 The Evolution of the Region of Interest Builder in the ATLAS experiment

The ATLAS readout architecture uses the concept of Regions of Interest (RoIs) identified by the hardware trigger for further analysis in trigger software. The High Level Trigger uses these RoIs to guide the retrieval of information from the readout system. Currently, a custom VME system, the RoI Builder (RoIB), collects the RoIs at 100 kHz. This talk describes the evolution of the RoIB to a PCIe card, the C-RORC, in a PC running dedicated software. The C-RORC implements 8 PCIe Gen 1 lanes with 12 optical links each running at 200 MB/s on 3 QSFP transceivers.

Speaker: Othmane Rifki (University of Oklahoma (US))

Othmane_Rifki_TWEPP_RoIB.pdf

60 Development of a sub-nanosecond time-to-digital converter based on field-programmable gate array

We present the design and the performance of a 24 channel time-to-digital converter with a variable time binning of down to 0.39 nsec based on a Xilinx Kintex-7 field-programmable gate array. The time measurement is provided by a multisampling scheme with quad phase clocks synchronized with external reference clock. The differential and integral nonlinearities have been measured to be less than the half of the time binning. The obtained performance of the time measurement is sufficiently high for various detectors in high energy physics, e.g. the monitored drift tube chambers at the ATLAS experiment.

Speaker: Yuta Sano (Nagoya University (JP))

TWEPP_poster.pdf

61 Versatile prototyping platform for Data Processing Boards for CBM experiment

The Data Processing Boards (DPB) are an important component of the CBM readout chain. Before the final, production versions of DPB may be designed, it is important to create a prototyping platform, to test and select appropriate hardware and firmware solutions. The Kintex based AMC FMC Carrier (AFCK) board is a versatile and open solution fulfilling those requirements, offering configurable high speed (up to 10 Gbps) connectivity. The paper describes the AFCK hardware, the firmware architecture, and the IP cores developed for different DPB prototyping tasks. Due to its versatility and openness the AFCK may be reused in other experiments.

Speaker: Dr Wojciech Zabolotny (Warsaw University of Technology, Institute of Electronic Systems (PL))

Zabolotny_ID25.pdf

62 A Fast Turn-on ADC Scheme and its Engineering Validation

In underground neutrino experiments, waveform digitization is often demanded at Giga-samples per second with occasional possible high instantaneous hit rate up to MHz range. As an alternative of regular flash ADC, a fast turn-on ADC scheme is presented in this paper. The ADC hibernates most of time during normal operation when the PMT is not hit and wakes up immediately to digitize the waveform once the detector channel is hit, which reduces total operating power significantly. The fast turn-on ability of a ramp-and-compare ADC implemented in an FPGA is tested.

Speaker: Jinyuan Wu (Fermi National Accelerator Lab. (US))

63 A multi-Gigabyte per Second PCI-Express Data Link for Real-Time DAQ Systems

A growing number of physics experiments requires DAQ systems with multi-Gbytes/s data-links. We developed a Direct Memory Access (DMA) engine compatible with the Xilinx PCI Express Gen2/3 core. The design comes with a Linux driver. Preliminary measurements with a Gen3 single-core have reached a throughput of up to 6.7 GBytes/s. We also intend to use this technology for direct communication between FPGA-based DAQ electronics and GPU memories (e.g. NVIDIA GPU-direct). This architecture finds its application in real-time DAQ systems and in low and high-level triggers for HEP experiments.

Speaker: Dr Michele Caselle (KIT)

poster_Caselle_DMA.pdf

64 FPGA implementation of PCI-express bifurcation for high-throughput data acquisition

The experiments at the LHC are undergoing a massive design upgrade to increase their data-taking capacities in the coming years, in anticipation of higher luminosity and new running conditions. For some experiments, the requirement of 100Gbps of readout bandwidth per readout unit has driven the adoption of PCI-express Gen3 as the main readout protocol. Limitations of current FPGA silicon to 8 lanes per interface require exploiting multiple interfaces to achieve the desired performance. In this work we study how PCI-express lane bifurcation could be exploited to overcome this limitation while minimizing BOM and layout complexity.

Speaker: Paolo Durante (CERN)

poster.pdf

65 Construction, Testing, Installation, Commissioning and Operation of the CMS Calorimeter Trigger Layer-1 CTP7 Cards

The CMS Phase 1 Calorimeter Trigger Upgrade Layer-1 CTP7 Card installation, commissioning and operation are described. The monitoring and performance of this system and interfaces are also covered.

Speaker: Ales Svetek (University of Wisconsin (US))

Svetek_TWEPP_Poster.pdf

66 Design of Si-Photonic structures and evaluation of their radiation hardness dependence on design parameters

A silicon photonic chip for radiation resistance evaluations has been designed and is currently being fabricated in an ePIXfab multi-project wafer run at imec. The chip contains custom-designed Mach-Zehnder modulators, pre-designed “building-block” modulators and photodiodes as well as various passive test structures. The simulation of the custom Mach-Zehnder modulators and the design flow of the chip is presented. We also plan to report on first measurement results of the modulators’ radiation hardness as a function of total ionizing dose.

Speaker: Marcel Zeiler (CERN)

TWEPP2015-Poster-SiPhotonicDesign-Zeiler.pdf

67 High Speed Data Transmission on Small Gauge Cables for the ATLAS Pixel Upgrade

Data transmission requirements for the upgrade of the ATLAS Pixel detector will be difficult to meet. The expected trigger rate and occupancy imply multi-gigabit per second transmission rates but radiation levels immediately at the detector preclude completely optical solutions. Electrical transmission for a short distance will be necessary to move optical components to a safer area. We have evaluated electrical transmission over short distances to determine the minimum size cable capable of 1-5 Gbps. Test results indicate multi-gigabit bandwidth is achievable with very small cables. Results for various low-mass cable configurations and bandwidths will be presented.

Speaker: Alex Grillo (University of California,Santa Cruz (US))

SCIPP ATLAS Data Poster v. 6.pdf

68 A Silicon Photonic Wavelength Division Multiplex System for High-Speed Data Transmission in Detector Instrumentation

Current and future particle physics or photon science detectors easily generate raw data rates of hundreds of Tbit/s. Even with massive local data reduction these data cannot be read out with current optical links. We propose a new optical data transmission system based on wavelength division multiplexing (WDM) with multiple monolithically integrated Mach-Zehnder modulators and optical multiplexers. The first demonstrator currently under development aims for a data rate of 160 GBit/s per fiber, scalable to 5 Tbit/s and beyond. Additionally our recently developed silicon photonic electro-optic modulators and Echelle gratings as WDM multiplexers are presented.

Speaker: Piotr Skwierawski (KIT)

Schneider_ID107.pdf

69 Board-mount miniature optical transmitters and transceivers for detector readout in particle physics experiments

MTx is a dual-channel optical transmitter. MTRx is a transceiver. They are custom developed, small form-factor, low mass and radiation tolerant for detector front-end in particle physics. A custom light-coupling fixture connects fibers of LC ferrules. MTx and MRTx are board-mount and 5.9 mm tall. The driver ASIC is LOCld developed for the ATLAS Liquid Argon Calorimeter trigger upgrade. The receiver uses GBITA developed in the GBT project. The transmitting and receiving data rates are 8 Gbps and 4.8 Gbps. Designs of LOCld, MTx and MTRx together with test results will be presented.

Speaker: Datao Gong (Southern Methodist Univeristy)

Poster MTx.pdf

70 Transmission Lines Implementation on HDI Flex Circuits for the CMS Tracker Upgrade

The CMS tracker upgrade at HL-LHC relies on hybrid modules build on high density interconnecting flexible circuits. They contain several readout ASICs having high speed digital ports required for configuration and data readout, implemented as SLVS differential pairs. This paper presents the connectivity requirements on the CMS tracker hybrids; it compares several transmission line implementations in terms of board area, achievable impedances and expected crosstalk. The properties obtained by means of simulations are compared with measurements made on a dedicated test circuit. The different transmission line implementations were tested using a custom 65nm SLVS driver and receiver prototype ASIC.

Speaker: Mark Istvan Kovacs (CERN)

TWEPP-15 Poster Transmission lines on HDI_v5.pdf

71 Low-Cost Bump-Bonding Process for High Energy Physics Pixel Detectors

Karlsruhe Institute of Technology (KIT) is one of the module production centres for the upgrade of the CMS pixel detector (phase 1). We will present recent developments of high-density low-cost bump-bonding technologies for both single prototype ICs and mass-production. In addition we will discuss our latest results on high-density copper pillar, gold-stud and Precoat-by-Powder Sheet (PPS) bumping technologies. Furthermore a new low-temperature bonding process for irradiated silicon sensors and Cd(Zn)Te sensors will be presented. Process optimization and production quality control methods will be discussed as well.

Speaker: Dr Michele Caselle (KIT - Karlsruhe Institute of Technology (DE))

poster_Caselle.pdf

72 Polyurethane spray coating of aluminum wire bonds to prevent corrosion and suppress resonant oscillations

Unencapsulated aluminum wedge wire bonds are common in particle-physics pixel and strip detectors. Industry-favored bulk encapsulation is eschewed due to the range of operating temperatures and radiation. Wire bond failures are a persistent, source of tracking detector failure Unencapsulated bonds are vulnerable to condensation-induced corrosion, particularly when halides are present. Oscillations from periodic Lorenz forces are documented as another source of wire bond failure. Spray application of polyurethane coatings, performance of polyurethane-coated wire bonds after climate chamber exposure, and resonant properties of PU-coated wire bonds and their resistance to periodic Lorenz forces will be described.

Speaker: Prof. Joseph Izen (University of Texas at Dallas)

izen_ID_195 typo-fixed.pdf

18:30 City boat tour

Wednesday 30 September

Invited Plenary

Convener: Christophe De La Taille (OMEGA (FR))

73 High resolution timing detectors and electronics: an overview

In the last decade the interest towards radiation detectors combining good time resolution (100 ps rms or below) and high channel density has significantly increased. ASICs implemented in deep submicron CMOS technologies and latest generation FPGAs allow to confine the error introduced by the readout electronics to a few ps. The main challenges are thus expected to come from the sensor and/or system level issues. In the presentation the key factors limiting the detector time resolution are discussed, with emphasis on the interplay between the sensor and its front-end. Significant developments in the field of high-resolution, high-granularity timing systems are reviewed.

Speaker: Angelo Rivetti (Universita e INFN Torino (IT))

TimingRivettiFinal.pdf

Trigger

Convener: Wesley Smith (University of Wisconsin (US))

74 Trigger architecture of the SuperNEMO experiment

SuperNEMO is the next-generation (0νββ) experiment based on a tracking plus calorimetry technique. The demonstrator is made of a calorimeter (712 channels) and a tracking detector (6102 channels). These detectors front-end electronics use an unified architecture. The trigger system has for the calorimeter part 2 trigger thresholds, for the tracker part the possibility of a second triggering for a delayed particle. The calorimeter and tracker can operate separately. We have an overlap between the zoning of the calorimeter and the tracker. The final trigger decision is made considering spatial coincidences between hits from the calorimeter and tracker detectors.

Speaker: Jihane Maalmi (Laboratoire de l'Accelerateur Lineaire (FR))

SuperNemo_Presentation_TWEPP_2015_Maalmi.pdf

75 The Phase-1 Upgrade of the ATLAS First Level Calorimeter Trigger

The ATLAS level-1 calorimeter trigger pursues a series of upgrades in order to face the challenges posed by the upcoming increase of the LHC beam energy and luminosity. The hardware built during the Phase-1 upgrade will be installed in 2018. The calorimeter data will be available with a tenfold increase of granularity which allows to employ more sophisticated identification algorithms. To cope with this increase of input data, an entirely new custom electronics processing system will be built exploiting the technological advances in the design of complex PCBs, powerful FPGAs, new crate technologies and high speed optical interconnects.

Speaker: Reinhard Schwienhorst (Michigan State University (US))

2015-09 TWEPP ATLAS L1Calo Phase 1.pdf

ASICs

Convener: Christophe De La Taille (OMEGA (FR))

76 Front end Optimization for the Monolithic Active Pixel Sensor of the ALICE Inner Tracking System Upgrade

ALICE plans to replace its Inner Tracking System in 2018 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented.

Speaker: Daehyeok Kim (Yonsei University (KR))

TWEPP_2015_Daehyeok.pdf

77 Charge Collection Properties of a Depleted Monolithic Active Pixel Sensor using a HV-SOI process

We have fabricated and tested a new 0.18 um SOI CMOS monolithic pixel sensor using the XFAB process. In contrast to most SOI technologies, this one provides a double well structure, which shields the thin gate oxide transistors from the Buried Oxide. This in addition with the particular geometry between transistors and BOX makes the technology promising. The process allows the use of high voltages, which are used to partially deplete the substrate. A fully depleted substrate could be achieved after thinning. Thus the fabricated device is especially interesting for applications in extremely high radiation environments, as LHC experiments.

Speaker: Sonia Fernandez Perez (CERN)

TWEEP2015_SFernandez.pdf

10:40 Coffee break

Trigger

Convener: Wesley Smith (University of Wisconsin (US))

78 Track Finding in CMS for the Level-1 Trigger at the HL-LHC

The High Luminosity LHC (HL-LHC) will deliver luminosities of up to 5x10^34 cm^2/s, with an average of about 140 overlapping proton-proton collisions per bunch crossing. These extreme pileup conditions place stringent requirements on the trigger system to be able to cope with the resulting event rates. A key component of the CMS upgrade for HL-LHC is a track trigger system which would identify tracks with transverse momentum above 2 GeV already at the first-level trigger. This talk presents the status of proposals for implementing the L1 tracking in conjunction with the planned upgrade for the silicon tracker of the CMS experiment. The expected performance and the use of L1 tracks for triggering is discussed.

Speaker: Mark Pesaresi (Imperial College Sci., Tech. & Med. (GB))

L1TF_TWEPP2015.pdf

ASICs

Convener: Christophe De La Taille (OMEGA (FR))

79 Prototyping of an HV-CMOS demonstrator for the High Luminosity-LHC upgrade

HV-CMOS sensors can offer important advantages for large area tracking systems in high energy physics experiments. Their use in future collider experiments (HL-LHC) will depend on the capacity to sustain the anticipated radiation levels. This contribution presents the design and preliminary measurements of an HV-CMOS pixel demonstrator in the ams 0.35 µm HV-CMOS technology for the ATLAS upgrade. The readout is compatible with the FEI4 ASIC. To increase the depletion region, wafers with moderate/high resistivities have been used. Various alternatives are implemented with different gain, speed, number of readout stages and output type.

Speaker: Eva Vilella (University of Liverpool)

2015_09_TWEPP_Vilella.pdf

80 Development on CMOS MAPS devices for the ATLAS Phase-II Strip Tracker Upgrade

ATLAS is currently studying the use of CMOS MAPS devices as a replacement for the baseline silicon strip sensors for the Phase-II Strip Tracker Upgrade. One of the key aspects is to establish whether the radiation hardness is suitable for the HL-LHC environment. Two different technologies are being studied: High-Voltage CMOS and High-Resistivity CMOS. Several test chips have already been manufactured. We present the latest results from non-irradiated and irradiated sensors including test beam results and give an outlook on the next steps.

Speaker: Todd Brian Huffman (University of Oxford (GB))

TWEPP2015ToddD.pdf

TWEPP2015ToddD.pptx

81 Prototype active silicon sensor in LFoundry 150nm HV/HR-CMOS technology for ATLAS Inner Detector Upgrade

The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of the inner tracking detectors. A possible solution is to use active silicon sensors taking advantage of commercial HV/HR-CMOS technologies. Current ATLAS R&D programme is qualifying a few commercial technologies it terms of suitability for this task. During this talk a prototype designed in one of them (LFoundry 150nm process) will be discussed – the chip architecture will be described, including different pixel types incorporated into designed, followed by simulation and measurement results.

Speaker: Piotr Rymaszewski (Universitaet Bonn (DE))

twepp2015_ccpd_lf.pdf

twepp2015_ccpd_lf.pptx

Systems, Planning, installation, commissioning and running experience

Convener: Wesley Smith (University of Wisconsin (US))

82 Deployment of the CTA AMC as Backend for the CMS Pixel Detector

This contribution will highlight the deployment of the CTA AMC as backend for the CMS Phase1 pixel detector that will run on a fully digital 400Mbps optical read-out link. The system architecture, the actual hardware and experiences with test systems and a pilot system installed in CMS will be presented.

Speaker: Georg Auzinger (CERN)

TWEPP_Auzinger.pdf

83 First Performance Results of the ALICE TPC RCU2

This paper presents the first performance results of the ALICE TPC Readout Control Unit2 (RCU2). With the upgraded hardware typology and the new readout scheme in FPGA design, the RCU2 is designed to achieve twice the readout speed of the first RCU. Design choices such as using the flash-based Microsemi Smartfusion2 FPGA and applying mitigation techniques in interfaces and FPGA design ensure a high degree of radiation tolerance. This paper presents the system level irradiation test results as well as the first commissioning results of the RCU2. Furthermore, it will be concluded with a discussion of the planned updates.

Speaker: Chengxin Zhao (University of Oslo (NO))

TWEPP 2015 CZ_V1.8.pdf

TWEPP 2015 CZ_V1.8.pptx

12:25 Lunch

Invited Plenary

Convener: Ken Wyllie (CERN)

84 SEU Mitigation Techniques for SRAM based FPGAs

Since the Wright brothers first powered flight 112 years ago, aircraft have become incredibly capable machines with an amazing safety record. Unfortunately, there are still incidents and accidents, but don’t worry, the airlines provide you with a life jacket! Since Xilinx introduced their first device 30 years ago, FPGAs are up to 10,000 times larger and tens of millions of them are used throughout the world (including those flying in aircraft). How susceptible are FPGAs to SEU and what will you provide and do should the worst happen?

Speaker: Ken Chapman (Xilinx)

Chapman_ID240.pdf

Chapman_ID240.pptx

Systems, Planning, installation, commissioning and running experience

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

85 The STAR Heavy Flavor Tracker PXL detector readout electronics

The Heavy Flavor Tracker (HFT) is a recently installed micro-vertex detector upgrade to the STAR experiment at RHIC, consisting of three subsystems with various technologies of silicon sensors arranged in 4 concentric cylinders. The two innermost layers of the HFT close to the beam pipe, the Pixel (“PXL”) subsystem, employ CMOS MAPS technology that integrates the sensor, front-end electronics, and zero-suppression circuitry in one silicon die. This talk will present selected characteristics of the PXL detector part of the HFT and the hardware and firmware and software associated with the readout system for this detector.

Speaker: Joachim Schambach (University of Texas (US))

Schambach.pdf

Schambach.pptx

86 The readout electronics of the SciFi Tracker for LHCb detector upgrade

A new detector made of scintillating fibres read out by silicon photomultipliers (SiPM) is planned for the LHCb detector upgrade, foreseen in 2018/19. The development of a dedicated readout electronics in the harsh LHC environment bears challenges. Each SiPM generates 10.24Gb/s of data after the digitization leading to a data rate of 9.1Tb/s for the full detector. Such a large amount of data can not be reasonably processed by a computing farm. In this paper, we describe the readout scheme and the zero suppression algorithm used to reduce the data flow below 8Tb/s.

Speaker: Herve Chanal (Univ. Blaise Pascal Clermont-Fe. II (FR))

twepp2015.pdf

87 Front End Electronics for SiPM Readout in the Mu2e CRV Detector

The Mu2e experiment requires a very high efficiency (99.99%) Cosmic Ray Veto to reject events that mimic signals. The CRV covers an area of 323 sq. m and consists of 4 layers of extruded scintillator with WLS fiber readout and using SiPMs . To meet the strict requirements while maintaining a low cost, we designed new front end electronics that is simple, relatively inexpensive in small quantities and has very good performance. There are approximately 300 front end boards in the CRV system, each with 64 channels. This may be of interest to many groups using SiPMs.

Speaker: Paul Rubinov (Fermilab)

Rubinov_189.pdf

Rubinov_189.pptx

ASICs

Convener: Alessandro Marchioro (CERN)

88 Design and results of a 65 nm digital readout Macro Pixel ASIC (MPA) prototype with on-chip particle recognition for the Phase II CMS Outer Tracker upgrade

The High Luminosity LHC (HL-LHC) requires major upgrade to the CMS experiment. In particular, the Phase II CMS Tracker upgrade needs a completely new readout ASIC called Macro Pixel ASIC (MPA) for its Pixel-Strip modules. It will extract and digitise analogue signals from pixelated sensor and perform digital processing at 40 MHz frequency. The digital processing includes particle recognition based on transverse momentum discrimination, global event storage and position encoding. The first prototype of the ASIC was designed, fabricated and tested. The successful results obtained will be presented and will drive the final development of the project.

Speaker: Davide Ceresa (CERN)

MPA-Light_TWEPP.pdf

MPA-Light_TWEPP.pptx

89 A 128-channel event driven readout ASIC for the R3B Tracker

R3B is a detector with high efficiency, acceptance, and resolution for kinematically complete measurements of reactions with high-energy radioactive beams. Detectors track and identify radioactive beams onto and out from a reaction target. Three layers of double-sided stereoscopic silicon strips form the tracker detector which must provide precise tracking and vertex determination and in addition include energy and multiplicity measurements. The R3B ASIC has been manufactured and is intended for processing and digitising signals generated by ionising particles passing through the tracker. The ASIC processes signals and provides spatial, energy and time measurements. Test results will be presented.

Speaker: Mr Lawrence Jones (STFC Rutherford Appleton Laboratory)

R3B_TWEPP_2015_compressed.ppt

90 PACIFIC: The readout ASIC for the SciFi Tracker planned for the upgrade of the LHCb detector

PACIFIC is a 64 channel mixed-signal ASIC designed for the scintillating fiber (SciFi) tracker developed for the LHCb upgrade in 2018/19. It connects without interface to the 128 channel double dye SiPM arrays sensing the fibers. The analog processing begins with a current conveyor followed by a tunable fast shaper and a gated integrator. The signal is digitized with a 2bit nonlinear flash ADC operating at 40MHz. The results of every two channels are serialized and transmitted at 160MSa/s. The power consumption has been kept below 8mW/channel. PACIFIC has been designed using a 130nm CMOS technology.

Speaker: Jose Mazorra De Cos (Instituto de Fisica Corpuscular (ES))

slides.pdf

16:05 Coffee break

Poster: Session 2

Conveners: Ken Wyllie (CERN), Mitchell Franck Newcomer (University of Pennsylvania (US))

91 Design of a Constant Fraction Discriminator for the VFAT3 front-end ASIC of the CMS GEM detector

In this work the design of a Constant Fraction Discriminator (CFD) to be used in the VFAT3 chip, currently under design for the read-out of the Triple-Gem detectors of the CMS experiment, is described. Simulations show that it is possible to extend the front-end shaping time to fully integrate the detector signal charge whilst maintaining optimal timing resolution using the CFD technique. A prototype chip containing 8 CFDs was implemented in 130nm CMOS technology to prove the effectiveness of the architecture before its integration in the VFAT3 chip. The CFD design and test results will be shown.

Speaker: Flavio Loddo (INFN-BARI)

Loddo_ID17.pdf

92 Development and experimental study of the Read-out ASIC for Muon Chambers of the CBM Experiment

The measurement results of the front-end ASIC for GEM detectors for Muon Chambers in the CBM experiment are presented. The MUCH ASIC was designed and prototyped via Europractice by means of the 0.18 um CMOS MMRF process of UMC (Taiwan). The parameters of the analog channels, including the CSA, fast and slow shapers, discriminators were measured. The channels provide a sufficient dynamic range of 100 fC, low power consumption of 10 mW and ENC of 1000 el at 50 pF detector capacitance. The further plans on the chip development is also discussed.

Speaker: Mr Evgeny Malankin (NRNU MEPhI)

PosterTWEPP.pdf

93 High speed readout solution for single-pixel-photon counting ASICs

We present a flexible, high speed readout system for the high-frame-rate photon-counting ASICs. The solution was implemented in an ASIC with 128 x 256 pixel matrix with dual 14-bit counter pixels, in 130 nm CMOS technology. In the presentation the details of the architecture and the test results will be shown. Currently the ASIC runs stable with 200 MHz input clock, while the tests with 500 MHz clock frequency and DDR mode are ongoing.

Speaker: Robert Szczygiel (AGH University of Science and Technology)

94 A 12-bit 60-MS/s 36-mW SHA-less Opamp-Sharing Pipeline ADC in 130nm CMOS

This paper presents a 12-bit 60-MS/s SHA-less opamp-sharing pipeline analog-to-digital converter implemented in a 0.13-µm CMOS technology. A switch-embedded dual-input current-reused operational transconductance amplifier with an overlapping two-phase clocking scheme is proposed to achieve low power and eliminate memory effects. The ADC achieves a signal-to-noise and distortion ratio of 64.9 dB and a spurious-free dynamic range of 77.1 dB at 60 MS/s. It occupies 2.3 mm2 area and consumes 36 mW power under a 1.2-V supply.

Speaker: Prof. Jinghong Chen (University of Houston)

Poster ADC.pdf

95 A front-end ASIC for ionising radiation monitoring with femto-amp capabilities

An ultralow leakage current Application Specific Integrated Circuit (ASIC) called Utopia (Ultralow Picoammeter) has been designed and fabricated in AMS 0.35 $\mu$m CMOS, in order to be used as the front-end for ionising radiation monitoring at CERN. It is based on the topology of a Current to Frequency Converter (CFC) and demonstrates a wide dynamic range of almost 7 decades without range changing. Because of its design aiming in ultralow input leakage current and the ESD protection leakage current compensation, input currents as low as 50 fA can be measured.

Speaker: Mrs Evgenia Voulgari (CERN)

twepp_poster_utopia.pdf

96 Pixel front-end with synchronous discriminator and fast charge measurement for the upgrades of HL-LHC experiments

Pixel detectors for HL-LHC experiments require the development of a new generation front-end chip to stand unprecedented radiation levels, very high hit rates and increased pixel granularity. A very compact, low power, low threshold very front-end design in 65nm CMOS technology is described. It contains a synchronous comparator with output offset storage threshold compensation technique. The latch can be turned into few hundred MHz local oscillator using an asynchronous logic feedback loop to implement fast time-over-threshold counting. A first prototype has been submitted in October 2014 and characterized: measurements and first irradiation results are presented.

Speaker: Ennio Monteil (Universita e INFN Torino (IT))

TWEPP_Poster.pdf

97 LOCx2, a low-latency, low-overhead, 2 × 5.12-Gbps serializer ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade

We present the design and test results of LOCx2, a high-speed serializer ASIC for detector readout in the ATLAS Liquid Argon Calorimeter trigger upgrade. LOCx2 consists of two channels. Each encodes the ADC data with an overhead of 12.5% and transmits serial data at 5.12 Gbps. The ASIC is fabricated with a commercial 0.25-µm Silicon-on-Sapphire CMOS technology and is packaged using QFN100. LOCx2 consumes 850mW of power and achieves less than 10-12 bit error rate with a latency of less than 38 ns.

Speaker: Datao Gong (Southern Methodist Univeristy)

20150918 Poster LOCx2.pdf

20150918 Poster LOCx2.ppt

98 Simulation of Digital Pixel Readout Chip Architectures for the LHC Phase 2 Upgrades with a SystemVerilog-UVM Verification Environment

The SystemVerilog-UVM simulation and verification platform VEPIX53, developed by the RD53 collaboration, is being used for the study and optimization of digital pixel chip architectures at behavioral level. The stimuli used by the framework can be generated internally using pre-defined hit classes or can also be imported from external CMS and ATLAS Monte Carlo detector simulations, featuring very high rate ($\sim2-3$ GHz/cm$^2$). VEPIX53 simulations produce statistics on inputs and enable architecture study through monitoring of design under test performance. A dedicated generic pixel chip model is being described at behavioral level for evaluating different architectures.

Speaker: Elia Conti (CERN)

twepp2015-poster-eliaconti.pdf

99 A 12b Rad-Hard Digital Calibrated Single Slope ADC for LHC environment

The presented 12bit single slope ADC is part of a system (called GBT-SCA), aimed to sense and monitor electrical/physical parameters in the LHC experiments. Measurement accuracy has been achieved by the combination of an analog accurate ramp generation and a digital correction for offset and gain errors. Moreover, both analog and digital solutions have been adopted to guarantee rad-hard performance. A prototype has been fabricated in a 130nm CMOS technology and exhibits a maximum DNL/INL of 0.259 LSB and 1.87 LSB, respectively, for a power consumption of 800uW from 1.5V supply.

Speaker: Dr Tommaso Vergine (University of Pavia)

Poster_twepp_2015_09_28.pdf

100 Front-end electronics for Micro Pattern Gas Detectors with integrated input protection against discharges

One of the major problems that have to be addressed in the design of the front-end electronics for readout of MPGDs, is its resistance to possible random discharges inside active detector volume. This issue becomes particularly critical for the electronics built as ASICs implemented in a modern CMOS technology, for which the breakdown voltages are in the range of a few Volts, while the discharges may result in voltage spikes of even thousand of Volts. The paper presents test results of input protection structures integrated in the ASIC using an electrical circuit to mimic discharges in the detectors.

Speaker: Dr Tomasz Fiutowski (AGH University of Science and Technology (PL))

discharge.pdf

101 SALT, a dedicated readout chip for strip detectors in the LHCb Upgrade experiment

Silicon strip detectors in the upgraded Tracker of LHCb experiment will require a new readout 128-channel ASIC called SALT. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130~nm process and uses a novel architecture comprising of analog front-end and ultra-low power ($<$0.5~mW) fast (40~MSps) sampling 6-bit ADC in each channel. A prototype of first 8-channel version of SALT chip, comprising all important functionalities, was submitted. Its design and possibly first tests results will be presented.

Speaker: Krzysztof Piotr Swientek (AGH University of Science and Technology (PL))

Swientek_poster.pdf

102 Comparison of two fast, ultra-low power 10-bit SAR ADCs in CMOS 130 nm A and B technologies

The design and the preliminary measurements results of two ultra-low power 10-bit Successive Approximation Register (SAR) Analog to Digital converters (ADC) fabricated in two CMOS 130~nm technologies (process A and B) are presented and compared. Both prototypes are fully functional achieving a good linearity, with INL and DNL below 1~LSB, and a good effective resolution, with ENOB above 9 bits. The power consumption of both prototypes is below 1~mW at nominal sampling rate of 40 MS/s. For both ADCs the power consumption scales linearly with sampling rate.

Speaker: Jakub Moron (AGH University of Science and Technology (PL))

Comparison_of_two_10-bit SAR ADCs_poster_TWEPP2015.pdf

103 FE65_P2: Prototype Pixel Readout Chip in 65nm for HL-LHC Upgrades

The LHC Phase-II upgrade will lead to a significant increase in luminosity, which will bring new challenges for the operation of the inner tracking detectors. To handle those requirements, a new pixel readout chip is being developed, within the RD53 collaboration taking advantage of the reduced feature size of 65nm technology. A 64x64 pixels (50 um pitch) prototype chip, introducing the concept of analog “islands” surrounded by a “sea” of digital gates, is being presented. The new analog frontend, isolation strategy, readout architecture and digital on top mixed-signal design flow will be discussed in detail.

Speaker: Tomasz Hemperek (Universitaet Bonn (DE))

FE65_P2_Prototype_TWEPP2015.pdf

104 First large volume characterization of the QIE10/11 custom front-end integrated circuits

The CMS experiment at the CERN Large Hadron Collider will upgrade the photon detection and readout systems of its barrel and endcap hadron calorimeters (HCAL) through the second long shutdown of the LHC in 2018. A central feature of this upgrade is the development of two new versions of the QIE (Charge Integrator and Encoder), a Fermilab-designed custom ASIC for measurement of charge from detectors in high-rate environments. For the first time, the characteristics and performance of the new QIE and their related chip-to-chip variations as measured in a sample of 20,000 chips is described.

Speaker: Daryl Hare (Fermi National Accelerator Lab. (US))

105 Radiation hard Regulator circuits for the ALICE ITS Upgrade

In the ALICE ITS upgrade project[1], serial powering of the modules of the detector is proposed. Serial powering scheme has its own advantages: It brings power at low currents and high voltage drastically reducing material budget. Serial powering of detectors has been proposed before[2]. A shunt LDO is designed for this purpose to regulate the power. The ITS is in radiation environment (~100 kRad). The shunt regulator and other building blocks were designed in Towerjazz 180 nm technology as a test chip named ALPOSE. This work will present the electrical characterization and radiation results of ALPOSE.

Speaker: Deepak Gajanana (NIKHEF)

106 65k pixel X-Ray camera module of 75µm pixel size

We present X-Ray camera consisting of hybrid pixel detector working in SPC mode. The camera consists of hybrid pixel detector built from silicon sensor and two readout integrated circuits, each of which is a matrix of 128 x 256 pixels with 75µm pitch, designed in CMOS 130 nm. The camera communicates with the higher level system using Ethernet, USB 2.0 and a Camera Link (up to 640 MB/s). An Artix-7 FPGA is used for both Camera Link interface and integrated circuit specific communication at the frequency of up to 200MHz – programmed in single software platform.

Speaker: Piotr Maj (AGH UST)

107 Status Of The Central Logic Board Of The KM3NeT Neutrino Telescope

The KM3NeT Collaboration aims at the construction of a multi-km3 high-energy neutrino telescope in the Mediterranean Sea consisting of thousands of glass spheres, each of them containing 31 photomultiplier of small photocathode area. The readout and data acquisition system of KM3NeT has to collect, treat and send to shore, the enormous amount of data produced by the photomultipliers and the instrumentation. The electronic design includes a multiboot module which allows re-configuring the nodes of the telescope remotely from the shore station. All the modules and subsystems are controlled by two microprocessors and the embedded software

Speaker: David Calvo (IFIC)

108 Design and Electronics of the CBM Micro-Vertex-Detector

Reconstructing Open-Charm Particles with the CBM-Experiment requires an ultra-light Micro Vertex Detector (MVD) using CMOS Monolithic Active Pixel Sensors. These sensors have unique properties concerning spatial resolution, radiation hardness, and material budget. A full read-out chain was designed and prototyped, comprising a multi-purpose FPGA platform and specialized front-end electronics. A commercially available very thin single-layer flex cable will be used as electrical connections to the sensors. We are going to give an overview on the detector concept for the MVD including our latest results from building a full sized prototype of one quadrant.

Speaker: Mr Michael Wiebusch (Goethe Universität, Frankfurt)

Wiebusch_ID137.pdf

109 ATLAS Transition Radiation Tracker (TRT) Electronics Operation Experience at High Rates

The ATLAS Transition Radiation Tracker (TRT) is a gaseous drift tube tracker which combines continuous tracking capabilities with particle identification based on transition radiation. The TRT Data Acquisition system uses custom front-end ASICs and boards for trigger and timing control as well as data read-out. To prepare for LHC run 2, changes were made to support the increased ATLAS trigger rate of 100 kHz, increased TRT occupancy caused by higher LHC luminosity, and gas mixture changes in some TRT straw tubes. Radiation studies were performed following an observed gain loss at the front-end during the 2012 run.

Speaker: Khilesh Pradip Mistry (University of Pennsylvania (US))

Twepp_KM_final1.pdf

110 Evaluation of a commercial AdvancedTCA board management controller solution

The MicroTCA (MTCA) and AdvancedTCA (ATCA) industry standards have been selected as the hardware platform for the upgrade of the electronic systems of some experiments of the Large Hadron Collider (LHC). In this context, the electronics support group for experiments at CERN is running a technical evaluation project for xTCA equipment. As part of this activity, a commercial solution for an intelligent platform management controller (IPMC), an essential component of any ATCA blade design, is being evaluated. We validated the supported IPMC features, checked the interoperability and adapted the reference design for use on an existing ATCA carrier board.

Speaker: Julian Maxime Mendez (CERN)

111 The ALICE HLT Readout Upgrade for Run2

The ALICE High Level Trigger (HLT) is a computing cluster dedicated to the online reconstruction and compression of experiment data. The interfaces to the HLT are realized with FPGA based PCIe boards. HLT has replaced all of its previous interface boards with the Common Read-Out Receiver Card (C-RORC). This contribution describes the ALICE HLT C-RORC firmware upgrade for Run2, the extended preprocessing core for hardware based cluster finding, the software interface to the HLT data transport framework and the firmware revision management for automated deployment in the HLT cluster.

Speaker: Heiko Engel (Johann-Wolfgang-Goethe Univ. (DE))

poster.min.pdf

112 Preparing the hardware of the CMS Electromagnetic Calorimeter control and safety systems for LHC Run 2

The Detector Control System (DCS) of the CMS Electromagnetic Calorimeter (ECAL) has undergone significant improvements during the first LHC Long Shutdown (LS1). Based on the experience acquired during the first period of physics data taking of the LHC, several hardware projects were carried out to improve data accuracy, to minimise the impact of failures and to extend remote control possibilities in order to accelerate recovery from problematic situations. This paper outlines the hardware of the CMS ECAL DCS and safety systems and explains in detail the requirements, design and commissioning of the new hardware projects.

Speaker: Oliver Holme (ETH Zurich (CH))

Poster_174.pdf

113 LHCb RICH Upgrade: an overview on the photon detector and the electronics system.

This presentation is meant to summarize the photon detector chain designed for the Upgraded RICH detector for the LHCb experiment. The photosensitive surface is composed of 64-channel MaPMTS (R11265 or R12699, produced by Hamamatsu) coupled with an external read-out electronics. The front-end chip, the CLARO, is an 8-channel ASIC in AMS 0.35 $\mu$m CMOS technology. The CLARO is able to sustain a photon counting rate of 40 MHz, with a power consumption < 1 mW/channel. A 12-bit digital register allows to select thresholds, attenuation and gives information for testing and debugging.

Speaker: Lorenzo Cassina (Universita & INFN, Milano-Bicocca (IT))

201509_Twepp_Lisbona_EC+CLARO_Corrected.pdf

114 Instrument Readout for the European Spallation Source

The European Spallation Source (ESS) will be multi-disciplinary research centre based on the world’s most powerful neutron source. This new facility will be around 30 times brighter than today's leading facilities, enabling new opportunities for researchers in the fields of life sciences, energy, environmental technology, cultural heritage and fundamental physics. We summarise the key technical challenges facing us at the ESS focusing in particular on data collection and instrument timing.

Speaker: Dr Scott Daniel Kolya (ESS - European Spallation Source (SE))

115 Development and performance studies of TORCH readout electronics using custom MCPs in a test-beam

The TORCH detector is an R&D project to provide low-momentum particle identification, combining Time-Of-Flight and Cherenkov techniques to achieve pi/K separation up to 10 GeV/c. Based-on an existing scalable design, we have undertaken production and testing of a system and have instrumented a novel customized Micro Channel Plate (MCP) device with 128-channels. The development and the performance of the system which has been used in a test-beam will be reported. The communication and data alignment between the TORCH system and the TimPix3 telescope for track reconstruction will also be discussed.

Speaker: Rui Gao (University of Oxford (GB))

TORCH_Poster_TWEPP2015.pdf

116 Commissioning of the on-detector electronics of a novel GEM-based detector for the CMS experiment

New Gas Electron Multiplier (GEM) based detectors are developed in view of the forward muon system upgrade of the CMS experiment in Phase 2 of the LHC. With the prospective of the full installation of the detectors during the LHC long shutdown (LS) 2 in 2018/2019, a slice test will take place during the Year-End Technical Stop of 2016 with subsequent detector commissioning. This contribution will present the preparation status and plans, focusing on the development of the data acquisition system, detector monitoring, calibration and control tools.

Speaker: Yifan Yang (Universite Libre de Bruxelles (BE))

PosterTwepp15-v1 (1).pdf

117 Development of the 40 MHz readout for the upgraded LHCb VELO

The upgraded LHCb VELO (vertex detector) will be equipped with silicon hybrid pixel detectors reading out at 40 MHz. The high data rates will be handled by high-end computing servers installed with FPGA cards. The output stage of the ASIC will be equipped with a custom developed output serialiser capable of handling the high rates while operating at low power. The firmware development will be described together with the irradiation tests of the output stage prototype.

Speaker: Karol Hennessy (University of Liverpool (GB))

118 GBT Link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

The high-energy physics experiments at the CERN’s Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2020. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver)1 links. The present work discusses the GBT link performance study carried out on custom FPGA boards.

Speakers: Jubin Mitra (Department of Atomic Energy (IN)), Shuaib Ahmad Khan (Department of Atomic Energy (IN))

GBT_TWEPP15_v3.pdf

119 Hardware evaluation of Xilinx High Level Synthesis for building data readout systems – a CMS ECAL Data Concentrator Card case

The current production version of the CMS ECAL Data Concentrator Card (DCC) is implemented with 11 FPGA devices (Altera and Xilinx), all placed on a single 9U VME card. The development and verification of the DCC FPGA firmware have consumed considerable amount of engineering resources. We have observed in recent years a trend in availability of new engineering tools for FPGA programming. Most of them promise higher productivity than widely used hardware description languages such as VHDL and Verilog/SystemVerilog. In this study, we present an implementation of the CMS ECAL DCC using C/C++ and Xilinx Vivado HLS. Emphasis will be placed on the hardware evaluation of results.

Speaker: Michal Husejko (CERN)

MHusejko_HLS_poster_v2.pdf

120 Performance of the prototype readout system for the CMS endcap hadron calorimeter upgrade

The CMS experiment at the CERN Large Hadron Collider (LHC) will upgrade the photon detection and readout systems of its hadron calorimeters (HCAL) through the second long shutdown of the LHC in 2018. The upgrade includes new silicon photomultipliers (SiPMs), SiPM control electronics, signal digitization via the Fermilab QIE11 ASIC, data formatting and serialization via a Microsemi FPGA, and data transmission via CERN Versatile Link technology. The first prototype system for the endcap HCAL has been assembled and characterized on the bench and in a test beam. The design of this new system and prototype performance is described.

Speaker: Nathaniel Joseph Pastika (Baylor University (US))

121 The CMS Level-1 Trigger Barrel Track Finder

The CMS Drift Tube Track Finder (DTTF) is being upgraded to a uTCA system, called Muon Barrel Track Finder (MBTF), so that it can cope with the high backgrounds which are expected at high luminosity and high pile-up. This upgrade which further improves the reliability of the system will be commissioned for the LHC RUN-II. In contrast to the DTTF, the MBTF receives muon super-primitives which are produced from both the DT and RPC detectors of the barrel region. The upgrade program of the barrel involves two stages.

Speaker: Nikitas Loukas (University of Ioannina (GR))

nloukas_bmtf_poster.pdf

122 Processing of the Liquid Xenon Calorimeter’s signals for timing measurements.

For identification of neutron-antineutron pair production events in the CMD-3 experiment (BINP) near threshold is necessary to measure the particles flight time in the LXe calorimeter with accuracy of about few nanosecond. The duration of charge collection to the anodes is about 5mks, while the required accuracy of measuring of the signal arrival time is less than 1/1000 of that. Besides, the signal shapes differ substantially between events, so the signal arrival time is measured in two stages. To implement that, a developed special electronics performs waveform digitization and OnLine measurement of signals' arrival times and amplitudes.

Speaker: Mr Leonid Epshteyn (Budker Institute of Nuclear Physics)

123 NaNet-10: a 10GbE Network Interface Card for the GPU-based Low-Level Trigger of the NA62 RICH Detector.

A GPU-based low level (L0) trigger is currently integrated in the experimental setup of the RICH detector of the NA62 experiment to assess the feasibility of building more refined physics-related trigger primitives and thus improve the trigger discriminating power. To ensure the real-time operation of the system, a dedicated data transport mechanism has been implemented: an FPGA-based Network Interface Card (NaNet-10) receives data from detectors and forwards them with low, predictable latency to the memory of the GPU performing the trigger algorithms. Results of the ring-shaped hit patterns reconstruction will be reported and discussed.

Speaker: Andrea Biagioni (INFN)

poster_NaNet_twepp2015.pdf

124 Pulsar IIb Design, System Integration and Next-Generation Full Mesh ATCA Backplane Test Results

The Pulsar IIb is a custom ATCA full mesh enabled FPGA-based processor board which has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth interconnections. The design has been motivated by silicon-based tracking trigger needs for LHC experiments. In this talk we describe the Pulsar II hardware, our full-crate integration tests, the results of our 40G and 100G ATCA full mesh backplane performance tests, and the experience gained throughout this process.

Speaker: Jamieson Olsen (Fermilab)

TWEPP_P2B_Poster_2015-09-23.pdf

125 A New Way to Implement High Performance Pattern Recognition Associative Memory in Modern FPGAs

Pattern recognition associative memory (PRAM) devices are parallel processing engines which are used to tackle the complex combinatorics of track finding algorithms. PRAM implementation has been mostly done with ASIC for high pattern density. However, implementation of PRAM in FPGAs allow for quick iterations, making it an ideal hardware platform for designing and evaluating new PRAM features before committing to silicon. For example, modeling in FPGAs can bring the system interface to maturity much sooner and minimize the ASIC design cycles. In this talk we present our FPGA-based PRAM design that is optimized for modern FPGA architectures.

Speaker: Jamieson Olsen (Fermilab)

TWEPP_PRAM_Poster_2015-09-22A.pdf

126 The Level-0 Trigger of the NA62 Liquid Krypton Calorimeter and its performance during first data-taking activities in 2015.

The Liquid Krypton calorimeter of the NA62 experiment at the CERN SPS is an essential part of the photon-veto system. The Level-0 trigger of the calorimeter identifies electromagnetic clusters and provides their position, fine-time and energy information for the trigger decision. In this contribution we present the first results and performances of the full system during the physics data-taking run in 2015.

Speaker: Nicola De Simone (Universita e INFN Roma Tor Vergata (IT))

127 The upgrade of the CMS Global Trigger

The Global Trigger is the final step of the CMS Level-1 Trigger. Previously implemented in VME, it has been redesigned and completely rebuilt in microTCA technology, using the Virtex-7 FPGA chip family. It will allow to implement trigger algorithms close to the final physics selection. The new system is presented, together with performance tests undertaken in parallel operation with the legacy system during the initial months of Run II of the LHC at a beam energy of 13 TeV.

Speaker: Johannes Wittmann (Austrian Academy of Sciences (AT))

Poster_TWEPP2015_The_upgrade_of_the_CMS_global_trigger.pdf

128 Results from longevity studies of the on-detector readout of the CMS Electromagnetic calorimeter

The on-detector readout installed in the CMS Electromagnetic Calorimeter (ECAL) has been tested to resist the radiation environment expected for ten years of LHC operation. The Phase II upgrade programme of CMS foresees additional LHC operation at higher luminosities until about 2035. Qualification of the on-detector readout for this longer running time, for the existing electronics and for those elements that will be replaced prior to Phase II, is required. Accelerated ageing tests of the present electronics have been performed to achieve a total estimated lifetime of 40 years. These new results will be summarized in this presentation.

Speaker: Michael Planer (University of Notre Dame (US))

CMS_ECAL_electronics_longevity_study.pdf

129 Upgrade of the ALICE TPC FEE online radiation monitoring system

This paper presents the radiation monitoring system on the Readout Control Unit (RCU) of the the ALICE TPC Front End Electronics. In Run 1, Single Event Upsets (SEUs) in the configuration memory of the SRAM based FPGA were counted, and the results from different run periods with stable beam condi- tions are presented. For Run 2, a new RCU has been designed where the number of SEUs in dedicated SRAM memories are counted. The paper presents this solution and gives the results from the targeted irradiation campaigns.

Speaker: Chengxin Zhao (University of Oslo (NO))

TWEPP15_RadMon_poster_r5.pdf

130 Development of a Radiation-Tolerant Component for the Quench Protection System

The increase of the Large-Hadron-Collider (LHC) luminosity over the next years will also increase the levels of ionizing radiation in the accelerator surroundings. Critical systems like the QPS need to be upgraded for higher radiation tolerance. A high resolution ADC for a future QPS component was tested for its radiation tolerance using a 230MeV proton beam up to a dose of 3.4kGy. The error modes discovered were analysed and countermeasures to mitigate them were developed. To validate these countermeasures a prototype system utilizing them was tested. The results show a sufficient suppression of 99% of all errors.

Speaker: Oliver Bitterling (Technische Universitaet Darmstadt (DE))

TWEPP2.pdf

131 COTS ADC for the Accelerator Radiation Environment

The analog to digital converter (ADC) is a component that is widely used in high energy physics. In recent years commercial off the shelf ADCs has become increasingly tolerant to ionizing radiation, likely a side effect of their implementation as a small feature size integrated circuit. In this presentation we report on recent irradiation results of COTS ADCs that can potentially be used in the detector readout electronics as well as for accelerator instrumentation. Two components, the ADS5272-SP and ADS52J90 were extensively tested and we report on the measurements performed.

Speaker: Helio Takai (Brookhaven National Laboratory (US))

132 Triggering on electron, jets and tau leptons with the CMS upgraded calorimeter trigger for the LHC RUN II

The design of the upgraded CMS Level-1 calorimeter trigger is based on a novel concept the Time Multiplexed Trigger (TMT). In this design there are nine main processing nodes each of which receives the data from an entire event. The nine processing nodes are fed data from a TMT switch which consists of 36 processors whose job is to collect fragments of events from each bunch crossing and construct entire events. This design is not different from that of the CMS DAQ and HLT systems. The advantage of this design is that there is no data sharing between the processing nodes each of which receives all the data from one event at high granularity and dynamic range. This opens up the possibility of designing highly sophisticated algorithms for the Level-1 trigger whose efficiency approaches the efficiency of the HLT algorithms. The details of the firmware and software design as well as the performance of the Level-1 trigger algorithms for the 2016 LHC run are presented in this poster.

Speaker: Alexandre Zabi (Centre National de la Recherche Scientifique (FR))

posterAZABI_TWEPP2015_TriggerCalo_final.pdf

133 Power Distribution for the ATLAS LAr Trigger Digitizer Board

The research activity for the design of the power distribution section of the ATLAS LAr Trigger Digitizer Board board (LTDB) will be presented. Many aspects concerning the radiation hardness and the ability to operate Point-of-load converters even in presence of high magnetic fields will be covered. Devices designed by CERN have been used and their capability for implementation on the ATLAS LTDB has been exploited with the aim to have a power distribution section with the required performances.

Speaker: Massimo Lazzaroni (Università degli Studi e INFN Milano (IT))

2015 - TWEPP2015.pdf

134 Performances of a Remote High Voltage Power Supply for the Phase II Upgrade of the ATLAS Tile Calorimeter

The experience gained in the working of the present High Voltage system of the Tile calorimeter and the new HLLHC constraints, in particular the increase in radiation, lead to the proposal of moving the embedded regulation system to a remote system in the counting room. This system is using the same regulation scheme as the present one and distributes the individual high voltage settings with multiconductor cables. The tests show that the remote system has the same performance in terms of regulation stability and noise, with a permanent access to the electronics. Moreover the implantation of new functionalities is easy.

Speaker: Francois Vazeille (Univ. Blaise Pascal Clermont-Fe. II (FR))

TWEPP2015_Vazeille5.pdf

135 Low Voltage Power for the ATLAS New Small Wheel Muon Detector

The New Small Wheel (NSW) is an upgrade for enhanced triggering and reconstruction of muons in the forward region of the ATLAS detector. The large Low Voltage power demands necessitate a point-of-load architecture with on-detector power conversion. We present final results from an extensive campaign to test commercial power devices in radiation and magnetic fields, and describe an alternate solution based on a radiation-hard power conversion ASIC produced by CERN. We detail the challenges and solutions in integrating this device into the New Small Wheel, and outline the full resulting power system.

Speaker: Ryan Christopher Edgar (University of Michigan (US))

136 Rad-Hard Vertical JFET switch for the HV-MUX system of the ATLAS upgrade ITk

This work presents a new silicon vertical JFET technology, based on the trenched 3D detectors developed at CNM, to be used as switches for the HV powering scheme of the ATLAS upgrade Inner Tracker. An optimization of the device characteristics is performed by TCAD simulations. Special attention has been paid to the on-resistance and the switch-off and breakdown voltages to meet the specific requirements of the system. The radiation damage mechanisms have been simulated to ensure that the devices will remain operational through the whole experiment life-time. Finally, a description of the technological process will be shown.

Speaker: Dr Pablo Fernandez Martinez (IMB-CNM (CSIC))

137 Experience from design, prototyping and production of a DC-DC conversion powering scheme for the CMS Phase-1 Pixel Upgrade

The CMS pixel detector will be exchanged during the technical stop 2016/2017. To allow the new pixel detector to be powered with the legacy cable plant and power supplies, a novel powering scheme based on DC-DC conversion is employed. After the successful conclusion of an extensive development and prototyping phase, mass production of 1800 DC-DC converters and power-related PCBs has started and will be finalized in September 2015. This contribution will summarize the lessons learned from the development of the power system for the Phase-1 pixel detector, and summarize the experience from the production phase.

Speaker: Katja Klein (Rheinisch-Westfaelische Tech. Hoch. (DE))

KatjaKlein_TWEPP2015.pdf

138 High dynamic range diamond detector acquisition system for beam wire scanner applications

A secondary particle shower acquisition system is under design for the CERN beam wire scanners upgrade. The new acquisition system is based on a polycrystalline diamond detector. Beam synchronous digitization will be performed in the tunnel, near the detector to fully exploit its large dynamic range and fast response. Two integrator ASICs (ICECAL and QIE10) are being characterized and compared for detector readout with the complete acquisition chain prototype, including the optical digital data transmission, at 4.8Gbps, with the GBT protocol and versatile link components (VTRx).

Speaker: Jose Luis Sirvent Blasco (University of Barcelona (ES))

TWEPP2015_Poster_Sirvent.pdf

139 Standardization of automated industrial test equipment for mass production of control systems

Power converters and their controls electronics are key elements for the operation of the CERN accelerator complex, having a direct impact on its availability. They must be designed to achieve a high Mean Time Between Failure (MTBF) and hardware reliability must be ensured by board level testing before hardware is assembled and installed. In this framework, the National Instrument PCI extension for Instrumentation (PXI) was chosen as standard platform for the development of testers. This paper reports on the design strategy and approach used focusing on the tester hardware, firmware and software development.

Speaker: Adriana Voto (Ministere des affaires etrangeres et europeennes (FR))

Poster_TWEPP2015_AdrianaVoto.pdf

Poster_TWEPP2015_AdrianaVoto.pptx

19:30 Conference dinner

Thursday 1 October

Invited Plenary

Convener: Philippe Farthouat (CERN)

140 Detector Developments at DESY for Free-Electron Lasers

For Free Electron Lasers the number of scattered photons per bunch is enough to record a full image. At the same time single photon sensitivity is required. An additional challenge at the European FEL stems from its time structures with 10 bunch trains per second each containing 2700 bunches (at 4.5 MHz). To meet these challenges the AGIPD-system has been under development. Full modules have now been produced and tested at Synchrotron Storage rings. An important part of the science performed at Free-Electron Lasers will be in the soft X-ray range, between 250 eV and 3 keV. PERCIVAL is a dedicated project to develop a CMOS based imager with up to 13 Mpixels, with 120 Hz frame-rate and having single photon sensitivity down to 250 eV. First back-thinned prototypes have been produced and extensively tested at various synchrotrons. Also these results will be discussed. Finally, future directions will be briefly presented.

Speaker: Heinz Graafsma

GraafsmaID241.pdf

GraafsmaID241.pptx

Systems, Planning, installation, commissioning and running experience

Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))

141 Performance of the Demonstrator System for the Phase-I Trigger Readout Electronics Upgrade of the ATLAS Liquid-Argon Calorimeters

For the Phase-I luminosity upgrade of the LHC, a higher granularity trigger readout of the ATLAS LAr Calorimeters is foreseen in order to enhance the trigger feature extraction and background rejection. The new readout system digitizes the detector signals, grouped into 34000 so-called Super Cells, with 12 bit precision at 40 MHz and transfers the data on optical links to the digital processing system, which extracts the Super Cell energies. A demonstrator version of the complete system has now been installed and operated on the ATLAS detector. Results from the commissioning and performance measurements will be reported.

Speaker: Nicolas Dumont Dayot (Centre National de la Recherche Scientifique (FR))

Twepp2015_Phase1Demonstrator_LAr.pdf

142 Qualification of the CMS Phase 1 Upgrade HF Front-end Electronics

The Phase 1 Upgrade of the CMS Forward Calorimeter requires the installation of custom and commercial electronics components into the CMS cavern where they are exposed to ionizing and hadronic radiation. We present the results of qualification tests on the most recent FPGAs from Microsemi (modified Igloo2 devices) and the QIE10 ASIC. The operation of the Igloo2 optical data link is demonstrated for both asynchronous transmission at 5 Gbps and LHC-synchronous operation as a control link following the CERN GBT protocol.

Speaker: Andrew James Whitbeck (Fermi National Accelerator Lab. (US))

QualificationOfCMSHFfrontend_TWEPP15.pdf

ASICs

Convener: Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

143 SAMPA Chip: a New ASIC for the ALICE TPC and MCH Upgrades

This paper presents the SAMPA ASIC that will be used in the ALICE upgrade for time projection chamber (TPC) and muon chamber (MCH) read-out frontend electronics. The SAMPA ASIC is being designed in 130nm CMOS technology with 1.2V nominal voltage supply. The SAMPA ASIC includes 32 channels, with selectable input polarity, and five possible combinations of shaping time and sensitivity. Each channel comprises a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC, followed by a DSP block. Experimental results for 18.5pF detector capacitance show an ENC of about 600e- and 20mV/fC sensitivity.

Speaker: Marco Bregant (Universidade de Sao Paulo (BR))

1509_TWEPP_Bregant.pdf

144 FATALIC: A dedicated Front-End ASIC for the Atlas TileCal Upgrade

A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

Speaker: Laurent Royer (Univ. Blaise Pascal Clermont-Fe. II (FR))

FATALIC_twepp_15_lisbonne_LR.pdf

FATALIC_twepp_15_lisbonne_LR.pptx

10:40 Coffee break

Systems, Planning, installation, commissioning and running experience

Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))

145 The NA62 spectrometer acquisition system

The NA62 main spectrometer consists of ~7000 straw tubes operating in vacuum. The front-end electronics is directly mounted on the detector. The front-end board provides the amplification, shaping, discrimination and time measurement of the analog signals from 16 channels. After digitization the data is sent to a VME 9U read-out board. The data, once matched with the trigger, is sent to the pc-farm and processed with the trigger level 1 algorithm. The front-end and read-out systems of the detector will be presented along with the first results of the detector performances.

Speaker: Vito Palladino (CERN)

Palladino TEWPP15 straw.pdf

Palladino TEWPP15 straw.pptx

146 A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgrade during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The main features and performance of the new readout system is presented.

Speaker: Cenk Yildiz (University of California Irvine (US))

twepp2015cyildiz.pdf

147 CMS DT Upgrade: The Sector Collector Relocation

The Sector Collector relocation is the first stage of the upgrade program for the Drift Tubes subdetector of the CMS experiment. It was accomplished during Long Shutdown 2013-2014, and consisted in the relocation of the second-level trigger and readout electronics from the experimental to the service cavern, relieving the environmental constraints and improving accessibility for maintenance and upgrade. Extending the electrical links would degrade reliability, so the information is converted to optical with a custom system capable of dealing with the DC-unbalanced data. Initially, present electronics are used, so optical-to-copper conversion has also been installed.

Speaker: Alvaro Navarro Tobar (Centro de Investigaciones Energ. Medioambientales y Tecn. - (ES)

TWEPP2015_final_anavarro.pdf

ASICs

Convener: Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

148 KLauS: A low power Silicon Photomultiplier Charge Readout ASIC in .18 UMC CMOS

We present the development of a low power Silicon Photomultiplier readout ASIC for imaging calorimetry detectors at future linear colliders. The analog front-end is designed to achieve sufficient SNR for single pixel signals using low gain SiPMs, while allowing charge measurements over the full sensor dynamic range. It consists of an input stage, two charge measurement branches and a fast comparator. A SAR ADC with a resolution of 10 bit digitizes the pulse height information. An additional pipelined SAR stage allows to increase the quantization resolution to 12 bit. Design details and first characterization measurements will be shown.

Speaker: Konrad BRIGGL (Heidelberg University)

twepp15_kbriggl.pdf

149 A low jitter PLL frequency synthesizer for high resolution TDCs in 65nm CMOS technology

A PLL has been designed for high frequency clock generation with only 280 fs RMS jitter. The integer N PLL multiplies a 40 MHz reference clock to 2.56 GHz. The PLL uses a low phase noise LC tank oscillator that has a tuning range from 2.4 GHz to 3.7 GHz with a phase noise of only 125 dBc/Hz @ 1 MHz and a power consumption of 5.7 mW. An all-digital automatic frequency calibration circuit is included to select the optimal frequency range of the VCO.

Speaker: Jeffrey Prinzie (KU Leuven (BE))

twepp_PL.pdf

twepp_PL.pptx

150 A fast multichannel, ultra-low power 10-bit ADC for readout of future particle physics detectors

The architecture, design, and preliminary measurements of multichannel 10-bit SAR ADC developed in CMOS 130~nm technology for readout systems of particle physics experiments, are presented. Other design issues like data serialization and high speed transmission are also discussed. The results of static and dynamic measurements, power consumption, crosstalk, etc., performed in multichannel operation of the ADC prototype are discussed. The measurements show a good effective resolution with ENOB above 9 bits, together with a good static linearity. The power consumption scales linearly with sampling frequency and at nominal sampling rate of 40MS/s it is below 1mW/channel.

Speaker: Marek Idzik (AGH University of Science and Technology (PL))

idzik_twepp2015_multiADC.pdf

12:25 Lunch

Invited Plenary

Convener: Prof. Lutz Feld (RWTH Aachen University)

151 Upgrade of the ALICE Silicon Tracker Using CMOS Pixel Sensors

ALICE is studying the physics of strongly interacting matter using nucleus-nucleus collisions at the CERN LHC. The ALICE Collaboration is preparing a major upgrade of the experimental apparatus, planned for installation in the second long LHC shutdown. A key element of the ALICE upgrade is the construction of a new, ultra-light, high-resolution Inner Tracking System (ITS). With respect to the current detector, the new ITS will significantly enhance the determination of the track impact parameter, the tracking efficiency at low transverse momenta, and the read-out rate capabilities. This will be obtained by seven concentric detector layers based on a 50-um thick CMOS pixel sensor with a pixel pitch of about 30x30um^2. I will present the design goals and layout of the new ALICE ITS, a summary of the R&D activities, with focus on the technical implementation of the main detector components.

Speaker: Luciano Musa (CERN)

twepp_2015_musa.pdf

Systems, Planning, installation, commissioning and running experience

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

152 Overview and Future Developments of the FPGA-based DAQ of COMPASS

COMPASS is a fixed-target experiment at the SPS at CERN dedicated to the study of hadron structure and spectroscopy. Since 2014, a hardware event builder consisting of nine custom designed FPGA-cards replaced the previous online computers increasing compactness and scalability of the DAQ. By buffering data, the system exploits the spill structure of the SPS averaging the maximum on-spill data rate over the whole SPS cycle. From 2016, a crosspoint switch connecting all involved high-speed links shall provide a fully programmable system topology and thus simplifies the compensation for hardware failure and improves load balancing.

Speaker: Dominik Steffen (Technische Universitaet Muenchen (DE))

presentation.pdf

153 A new approach to front-end electronics interfacing in the ATLAS experiment

For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2 a new approach will be followed for front-end electronics interfacing. The FELIX (Front-End Link eXchange) system will interface to links connecting to front-end detector and trigger electronics instead of the RODs (ReadOut Drivers) currently used. FELIX will function as a gateway to a commodity switched network built using standard technology (either Ethernet or Infiniband). In the paper the new approach will be described and results of the demonstrator program currently in progress will be presented.

Speaker: Andrea Borga (Nikhef National institute for subatomic physics (NL))

TWEPP2015_FELIX_Borga.pdf

154 Performances of the EUSO-Balloon electronics

The 24th of August 2014, the EUSO-BALLOON instrument went for a night flight for several hours, 40 km above Timmins (Canada) balloon launching site, concretizing the hard work of an important part of the JEM-EUSO collaboration started 3 years before. This instrument consists of a telescope made of two lenses and a complex electronic chain divided in two mains sub-systems: the PDM (photo detector module) and the DP (data processing). Each of them is made of several innovative elements developed and tested in a short time. This paper presents their performances before, during and after the flight.

Speaker: Pierre Barrillon (Laboratoire de l'Accelerateur Lineaire (FR))

balloon_launch_lowres_FromMichaelWille.avi

euso-balloon_PierreB.pptx

ASICs

Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))

155 Redundant SAR ADC architecture and circuit techniques for ATLAS LAr Phase-II upgrade

We present the architecture and circuit techniques of a 14-bit 80-MS/s split-SAR ADC in 65-nm CMOS with preliminary simulation results. By exploiting redundancy, SEE-related conversion errors can be efficiently detected and corrected at the architectural level by the added SEE-detection circuitry. The digital calibration also makes the overall ADC performance insensitive to transistor parameter variations, thus providing inherent TID immunity. The initial transistor-level simulation results revealed a ≥75-dB SNDR and a ≥90-dB SFDR, with a total power consumption of ≤30 mW.

Speaker: Yun Chiu (UT Dallas)

Chiu_ID68.pdf

Chiu_ID68.pptx

156 Development of a low power Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) in 130nm CMOS technology

The design and measurement results of a low power PLL and DLL prototypes for applications in particle physics readout systems are presented. The PLL was designed for frequency range 30MHz - 450MHz and 16 clock phases. Preliminary measurements show, that is functional and has period jitter ~6.7ps (RMS) at 160MHz. The DLL operates for input clock range 18MHz - 62MHz and generates 64 uniform clock phases. Its period jitter is ~3.2ps - 7.8ps (RMS). The power consumption of PLL at 160MHz is ~0.5mW, while the DLL consumes ~0.7mW at typical 40MHz input.

Speaker: Miroslaw Firlej (AGH University of Science and Technology (PL))

pll_dll_firlej.pdf

157 GBLD10+: A Compact Low-power 10 Gb/s VCSEL Driver IC

We report the design and implementation of a low-power and radiation-tolerant 10 Gb/s VCSEL Driver (GBLD10+) for High Energy Physics (HEP) applications. With new circuit techniques, the single-channel driver consumes 40 mW and occupies a compact size of 380 µm × 1730 µm including the PADs. These features allow multiple of driver ICs to be assembled side by side in a compact package, with each one directly wire bonded to one diode in a VCSEL array. This makes the GBLD10+ a suitable candidate for the Versatile Link which offers the flexibility in configuring multiple transmitters and receivers.

Speaker: Tao Zhang (SMU)

Tao_ID232.pdf

Tao_ID232.pptx

16:05 Coffee break

Systems, Planning, installation, commissioning and running experience

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

158 The PCIe-based readout system for the LHCb experiment

The upgrade of the LHCb experiment at CERN will implement a trigger-less readout system in which all the data are transported to the computing farm over 12000 optical links without hardware filtering. The event building and event selection is entirely operated in the farm. Another originality of the system is that data from the detector arrive directly in computers through a specially designed PCIe card called PCIe40. This presentation will explain these design choices and will describe the performance of the PCIe40 board and the overall system.

Speaker: Frederic Rethore (Centre National de la Recherche Scientifique (FR))

PCIe40 RS LHCb Exp3f[1].pdf

159 Common Readout Unit (CRU) – A new readout architecture for ALICE experiment

To cope up with the increasing luminosity of the Large Hadron Collider (LHC) at CERN, the ALICE experiment is planning for a major upgrade of the detectors, which is at present foreseen to start in 2018. The high interaction rate and the large event size results in an experimental data flow traffic of about 1 TB/s from the detectors to the on-line computing system. A dedicated Common Readout Unit (CRU) is proposed for data concentration, multiplexing and trigger distribution. We discuss the firmware design and implementation of CRU on the LHCb PCIe40 board.

Speakers: Jubin Mitra (Department of Atomic Energy (IN)), Shuaib Ahmad Khan (Department of Atomic Energy (IN))

CRU_TWEPP_15.pdf

CRU_TWEPP_15.pptx

160 MicroTCA and AdvancedTCA equipment evaluation and developments for LHC experiments

The MicroTCA (MTCA) and AdvancedTCA (ATCA) industry standards have been selected as the platform for many of the current and planned upgrades of the off-detector electronic systems of two of the LHC experiments at CERN. We present a status update from an ongoing project to evaluate commercial MTCA and ATCA components with particular emphasis on infrastructure equipment such as shelves and power-supplies. Shelves customized for use in the existing rack infrastructure have been tested, and electrical and cooling measurements and simulations were performed. Inhouse developments for an automated test system and for hardware platform management will be shown.

Speaker: Stefan Ludwig Haas (CERN)

xTCA-Project-TWEPP-Sep15-Final.pdf

161 The CMS TCDS Installation

The CMS Experiment is in the process of upgrading several of its detector systems. Adding more individual detector components brings the need to test and commission those components separately from existing ones so as not to compromise physics data-taking. The CMS Trigger, Timing and Control (TTC) system had reached the limit of the number of partitions that could be supported. A new Timing and Control Distribution System (TCDS) has been designed, built and installed in order to overcome this limit. The TCDS hardware and system will be described along with the experience gained from its installation and operation.

Speaker: Jan Troska (CERN)

TCDS_installation_TWEPP2015.pdf

Microelectronics User Group

Convener: Kostas Kloukinas (CERN)

162 News on Foundry Services

Speaker: Kostas Kloukinas (CERN)

MUG TWEPP2014 intro Kloukinas.pdf

MUG TWEPP2014 intro Kloukinas.pptx

163 Library Characterization Techniques for 65nm and 130nm Technologies

Speaker: Xavi Llopart Cudie (CERN)

LibCharctSeminar.pdf

LibCharctSeminar.pptx

164 TID Effects in 65nm Transistors: Summary of a Long Irradiation Study at the CERN X-rays Facility

Speaker: Federico Faccio (CERN)

TWEPP15_Faccio.pdf

165 Europractice EDA tools for the HEP community: 2015 update

Speaker: Emily van der Heijden (STFC)

166 Open Discussion

Friday 2 October

Invited Plenary

Convener: Philippe Farthouat (CERN)

167 ESA Microelectronic Developments for space

An overview of the development and deployment of a select key electronic components, like the microprocessor, digital signal processor and microcontroller for space ESA is presented. The development history of these specific components is outlined in view of the functional, performance, environmental requirements as well as commercial constraints.

Speaker: Richard Jansen (ESA)

ESA_Microelectronic_Developments_for_space_v5.pptx

ESA_Microelectronic_Developments_for_space_v5.pptx.pdf

Sentinel-2 Launch.mp4

Plenary: 1

168 Towards a 65nm Pixel Readout Chip for ATLAS and CMS High Luminosity Upgrades

For the Phase II Upgrade of both ATLAS and CMS experiments, a new pixel read-out chip needs to be developed to meet the requirements in terms of spatial resolution, data rate, and radiation tolerance. The RD53 research collaboration will develop a large area mixed signal ASIC in a 65nm CMOS technology. Special working groups focus on major design tasks like radiation tolerant design, top-level architecture, IP block development, analog front-end design etc. The status of the development tasks will be shown, which includes the design flow and read-out concept, and the development of specialized IP blocks.

Speaker: Hans Krueger (University of Bonn)

Towards a 65nm Pixel Readout Chip for ATLAS and CMS HL-LHC Upgrades rev2.pdf

Plenary: 2

169 DARE platforms: Past, present, future

Imec has been developing radiation hardened-by-design libraries with additional functionality using different CMOS technologies (.18 UMC and beyond). These DARE (Design Against Radiation Effects) platforms allow re-use, lower development times and risk of the design of circuits that need to withstand radiation. The paper gives an overview of the currently available platforms and their metrics and gives a view on plans for the future.

Speaker: Steven Redant (imec)

Redant_ID148.pdf

10:35 Coffee break

Plenary: 3

170 Operation of the enhanced ATLAS First Level Calorimeter Trigger at the start of Run-2

In 2015 the LHC will operate with a higher center-of-mass energy and proton beams luminosity. To keep a high trigger efficiency against an increased event rate, part of ATLAS Level-1 Calorimeter Trigger electronics have been re-designed or newly introduced (Pre-Processors, Merging Modules and Topological Processors). Additionally, to achieve the best possible resolution for the reconstructed physics objects, complex calibration and monitoring systems are employed. Hit rates and energy spectra down to channel level, based on reconstructed events, are supervised with the calorimeter trigger hardware. The performance of the upgraded Level-1 Calorimeter Trigger at the beginning of LHC Run-2 is illustrated.

Speaker: Marek Palka (Jagiellonian University (PL))

twepp_2015_mp.pdf

Plenary: 4

171 Upgrades to the CMS Level-1 calorimeter trigger

The CMS Level-1 calorimeter trigger is being upgraded in two stages to maintain performance as the LHC increases beam energy and instantaneous luminosity. In the first stage, improved algorithms including event by event pileup corrections are used. In the second stage, higher granularity inputs and a time-multiplexed approach allow for improved position and energy resolution. Data processing in both stages of the upgrade is performed with new, Xilinx Virtex-7 based AMC cards.

Speaker: Ben Kreis (Fermi National Accelerator Lab. (US))

Kreis_TWEPP.pdf

Close out

172 Close out

Speaker: Jorgen Christiansen (CERN)

TWEPP15-Closing.pdf

TWEPP15-Closing.pptx