The R3B silicon tracker is a three-layer silicon micro-vertex tracker, providing precise tracking, vertex determination and energy and multiplicity measurements. It is being built by a collaboration of the STFC and the universities of Liverpool, Manchester, Edinburgh and Surrey.
The 128-channel R3B ASIC reads out and digitises signals generated by particles passing through the silicon strip detector and uses a classic fast and slow signal path for timing and energy selection. The ASIC detects signals in the range 40keV-5MeV with a maximum data rate of 5 kHz/channel. The preamplifiers remove most of any signal charge from detector strips and the signal is filtered by CR-RC shapers to reduce noise. The pulses feed into the peak hold circuits where the signal amplitudes are saved prior to digitisation with a 12-bit successive-approximation-register ADC. A 32 deep FIFO holds the channel data until it can be read off chip.
Both polarities of signal are detected and likewise both polarities of leakage current compensated, up to 100nA. The preamplifier copes with a large range of input capacitance (0-80pF) due to the geometry of the detector strips and can recover quickly from signals greater than 20 times the normal range.
A comparator generates a time stamp (up to 5ns resolution) from the fast rising edge of the preamplifier signal, and another comparator generates energy decision from the output of the shaper. Any signal above the energy threshold also triggers the readout of neighbouring channels. Only channels hit by a particle with sufficient energy to trigger the timestamp comparator will generate a valid timestamp. Channels read out as neighbours are time-stamped by the energy threshold comparator.
A “validation” input is included which must be active for the hit to be marked valid for readout. This requires a data acquisition system that knows when to apply this control and it is used to filter out background signals which are not wanted and could swamp the ASIC with unwanted data.
An analogue multiplexer outputs the voltage from each hit channel to the ADC where it is converted to 12 bits. Each channel is dynamically reset once the signal has been saved. Digital data output from each hit channel includes the 12-bit energy, 15-bit timestamp and 7 bit channel address. An additional bit indicates whether the timestamp is valid.
Multiple chips are daisy-chained together with one chip acting as a master. An additional output from the ASIC is a 128 bit OR of all the hit channels which can be used as a trigger by the external system.
The three versions of the ASIC have been manufactured. Tests have shown that the first and second versions of the ASIC perform well, with some areas for improvement, and so a third version of the ASIC has been manufactured and is currently under test.