Universitaet Bonn (DE)
Author in the following contributions
- Charge Collection Properties of a Depleted Monolithic Active Pixel Sensor using a HV-SOI process
- Simulation of Digital Pixel Readout Chip Architectures for the LHC Phase 2 Upgrades with a SystemVerilog-UVM Verification Environment
- Prototype active silicon sensor in LFoundry 150nm HV/HR-CMOS technology for ATLAS Inner Detector Upgrade
- FE65_P2: Prototype Pixel Readout Chip in 65nm for HL-LHC Upgrades
