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Feb 15 – 19, 2016
Vienna University of Technology
Europe/Vienna timezone

Level Zero Trigger Processor for the ultra rare Kaon decay experiment - NA62

Not scheduled
Vienna University of Technology

Vienna University of Technology

Gusshausstraße 27-29, 1040 Wien
Board: 78
Poster Electronics


Mr Soldi Dario (Turin University - INFN)


The NA62 experiment is designed to measure the (ultra)rare decay $K^+ \rightarrow \pi \nu\bar{\nu}$ branching ratio with a precision of ~10% at the CERN Super Proton Synchrotron (SPS).The L0 Trigger Processor (L0TP) is the lowest level system of the trigger chain. It is hardware implemented using programmable logic. The architecture of the L0TP is completely new for an high energy physics experiment. It is fully digital, based on a standard gigabit ethernet communication between detectors and L0TP Board. The L0TP Board is a commercial development board, Terasic DE4, mounting an Altera Stratix IV FPGA. The primitives generated by sub detectors are sent asynchronously using the UDP protocol to the L0TP during the entire beam spill period (~5 seconds). The L0TP realigns in time the primitives coming from 7 different sources and manage the information of the time plus all the characteristics of the event as energy, multiplicity, position of hits, to select good events with a comparison with preset masks. It should guarantee a maximum latency of 1 ms. The maximum input rate is 10 MHz for each sub-detector, while the design maximum output trigger rate is 1 MHz. A complete trigger less parasitic acquisition of the primitives it is possible using mirroring switches to monitor the L0 behaviour. A first version of the L0TP was commissioned during the 2014 NA62 pilot run and it is used in the current data taking. A review of the trigger performance will be presented.

Primary author

Mr Soldi Dario (Turin University - INFN)

Presentation materials