11th Workshop on Electronics for LHC and future Experiments

A Silicon Strips Detector Readout Prototype Chip in 180 nanometer CMOS Technology

Not scheduled

1m

Heidelberg

Poster

Speaker

Mr Jean-Francois Genat (CNRS/IN2P3/LPNHE)

Description

A 16-channel readout chip for Silicon strips detectors has been designed in 180 nanometer CMOS technology and tested. It includes low-noise amplification, pulse shaping, sampling and threshold detection. An input referred noise of 190 + 12 electrons/picoFarad for an integration time of 3 microseconds has been measured, leading to an overall signal to noise ratio of 30 and a dynamic range of 75 Minimum Ionizing Particles at +/- 1.5 linearity, for a 60 centimeter long strip. Power dissipation is 350 microWatt per channel, area is 0.05 square millimeter.

Presentation materials

Paper

paper