11th Workshop on Electronics for LHC and future Experiments

Session

Parallel session A2

A2

13 Sept 2005, 14:15

Heidelberg

72. Evaluation of the Radiation Tolerence of SiGe Heterojunction Bipolar Transistors Under 24GeV Proton Exposure

Mr N. Spencer (UC Santa Cruz)

13/09/2005, 14:15

Oral

For the potential use in future high luminosity application in HEP (e.g. the LHC upgrade), we evaluated the radiation hardness of a candidate technology for the front-end of the readout ASIC for silicon strip detectors. The devices were test transistors of various geometries manufactured in the first generation, IBM SiGe 5HP process. Current gain as a function of collector current has been...

62. Irradiation tests of the complete ALICE TPC Front-End Electronics chain

Mr Ketil Røed (Faculty of Engeneering, Bergen University College, Norway)

13/09/2005, 14:40

Oral

The ALICE TPC Front End Electronics will be operated in a radiation field of up to 800 hadrons/cm2sec. SRAM-based FPGAs are used on the Front-End Cards (FEC) and the Read-out Control Units (RCU). Several irradiation tests of all components on the cards have ensured that the components selected are able to withstand the radiation environment, but have also shown that single event upsets...

97. A radiation-tolerant LDO voltage regulator for HEP applications

Dr Federico Faccio (CERN)

13/09/2005, 15:05

Power Management and Conversion

Oral

We have developed a radiation-tolerant Low Drop-Out (LDO) voltage regulator for applications in High Energy Physics experiments. The regulator outputs a fixed voltage of 2.5V, it provides a maximum current of 300mA with a drop-out as low as 150mV. The circuit incorporates over-current, over-voltage and over-temperature protection, and it can be disabled via a dedicated input pin....

76. The TRAcklet Processor chip for the ALICE TRD

Dr Venelin Angelov (KIP, Uni-Heidelberg)

13/09/2005, 15:30

Tracking

Oral

The ALICE TRD has over 1,2 million analog channels that will be digitized at 10MSPS with 10-bit resolution. We have developed a TRAcklet Processor (TRAP) ASICs implementing 22 extra low power ADCs, digital filters, four RISC processors with shared memory, slow control serial interface and fast parallel 4-in 1-out readout tree ports. Together with the preamplifier chip they build a...