11th Workshop on Electronics for LHC and future Experiments

Session

Parallel session A1

A1

13 Sept 2005, 11:00

Heidelberg

1. A VLSI Full Custom ASIC Front End for the Optical Module of NEMO Underwater Neutrino Detector

Dr Domenico Lo Presti (Catania University-Physics Department)

13/09/2005, 11:00

Custom Integrated Circuits

Oral

A cubic KM scale underwater neutrino detector requires thousands of photomultipliers whose signal must be acquired and transferred through an electro-optical cable to shore for analysis and storage. The transferrable power and data bandwidth of this cable is limited. The work described here has been developed in the context of the NEMO Collaboration with the aim of studying and...

46. Delay25, an ASIC for timing adjustment in LHC

Mr Hugo Furtado (CERN)

13/09/2005, 11:25

Oral

A five channel programmable delay line ASIC was designed, fabricated and tested. The IC features 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from process, supply voltage and temperature variations. The...

15. The 0.25um Token Bit Manager for CMS Pixel Readout

Mr Edward Bartz (Rutgers University)

13/09/2005, 11:50

Oral

To coordinate groupings of pixel readout chips, the Token Bit Manager (TBM), has been developed for the CMS experiment. The TBM will coordinate passing of the readout token around a group readout chips (ROC). In addition it supplies the DAQ with a header and trailer record to facilitate event recognition. Also present on the same chip is a Control Network Hub, which directs...

32. A current-based readout ASIC with on chip pedestal subtraction and zero suppression for a fast readout at a future collider

Mr Marcel Trimpl (Bonn University)

13/09/2005, 12:15

Oral

For a very fast readout of a DEPFET pixel matrix at the ILC (International Linear Collider) the 128 channel CURO II ASIC has been designed and fabricated in a 0.25 µm process. Due to the signal of the sensor being a current, the architecture of the chip is completely based on current mode (SI) techniques. This comprises double-correlated-sampling in the analog front end with...