Speaker
Description
Summary
The ATLAS New Small Wheels (NSW) Phase I Muon System upgrade will use Micromegas and small Thin Gap Chambers (sTGC) as both trigger and precision readout detectors. A new ASIC, the VMM, is being developed for the front ends of both of these detectors. The VMM is a sophisticated ASIC, System on Chip (SOC), providing digitized amplitude and time information as well as independent trigger paths for both detector systems. In this poster paper we describe the proposed use of this ASIC (and also the overall NSW electronics readout architecture) for the readout of the planned HL-LHC MDT detector upgrade. Details of the proposed architecture, bandwidth requirements, and plans for implementation will be presented. The similarity to the Phase I system and the resulting benefits will be stressed.