21–25 Sept 2009
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France
Europe/Paris timezone
<strong>The deadline for paper submission has been extended to 23 October 2009</strong>

Performance and comparison of custom serial powering regulators and architectures for SLHC silicon trackers

23 Sept 2009, 17:05
25m
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Oral Power, grounding and shielding Parallel Session B4 - Power, Grounding and Shielding

Speaker

Tomas Tic (RAL/ASCR)

Description

Serial powering is an elegant solution to power the SLHC inner trackers with a minimum volume of cables. So far R&D on serial powering for silicon strip modules was based on discrete commercial electronics. With the delivery of the first iteration of the ABCN-25 readout chip and the SPi serial powering interface chip, custom elements of shunt regulators and transistors became available. The combination of ABCN-25 and SPi can be used to implement three complementary serial powering architectures. The performance and features of the three architectures obtained with 20 chip and 10 chip ABCN-25 hybrids will be presented.

Summary

Serial powering is one of the few practical approaches to distribute power to the SLHC inner trackers with a minimum volume of cables. A number of integrated test structures (supermodules) with serial powering circuitry have been built and investigated over the last years with very promising results. The serial powering circuitry (shunt regulator, shunt transistors and LVDS buffers for AC coupling) was so far based on discrete commercial electronics.

To overcome this limitation in radiation-hardness and real-estate, various serial powering and power management blocks have been implemented in the first version of the ABCN-25 chip. In addition a dedicated serial powering chip, the serial powering interface (SPi) became available. Both ABCN-25 and SPi are realized in 0.25 um CMOS processes.

With these chips three complementary serial powering architectures can be realized. In one architecture the SPi regulator and shunt transistor act as a local power supply on the hybrid and the ABCN-25 internal shunt regulators are not used. This is conceptually the simplest implementation. It requires a robust shunt transistor layout. In another architecture, the SPi shunt regulator controls not a single shunt transistor but distributed shunt transistors in each ABCN-25. Finally, in a third architecture, SPi is not used and the shunt regulators and transistors implemented in ABCN-25 are operated in parallel.

These architectures are implemented on conventional copper Kapton flex hybrid prototypes with up to 20 ABCN-25 chips each. The hybrids were designed at Liverpool University for R&D on the ATLAS SLHC short strip tracker.

After a brief discussion of the architectures and their theoretical features, the characterization results will be presented and discussed. This includes regulator output voltage noise, dynamic impedance, and hybrid noise and noise occupancy as a function of temperature and current. Depending on the status of the measurements at the time of the conference, results on a full module or with a limited number of hybrids in series will be shown as well.

Authors

Mr Marc Weber (Rutherford Appleton Laboratory) Tomas Tic (RAL/ASCR)

Presentation materials