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TWEPP-09 Topical Workshop on Electronics for Particle Physics

→ Europe/Paris
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France
Francois Vasey (CERN)
Description

The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.

LHC experiments will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.

The purpose of the workshop is :

- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities

- to review the status of electronics for the LHC experiments

- to identify and encourage common efforts for the development of electronics

- to promote information exchange and collaboration in the relevant engineering and physics communities.

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  • Monday, 21 September
    • OPENING 1
      slides
      • 1
        Welcome 1
        Speaker: Francois Vasey (CERN)
        Slides
      • 2
        Welcome 2
        Speaker: Dr Christophe de La Taille (IN2P3/LAL Orsay)
        Slides
      • 3
        Research activities at Pierre & Marie Curie University
        Speaker: Paul INDELICATO (UPMC)
        Slides
      • 4
        Status and Perspective of Research at IN2P3
        Speaker: Etienne AUGE (IN2P3)
        Slides
      • 5
        Micro-Electronics at In2P3
        Speaker: Dr Christophe de La Taille (IN2P3/LAL Orsay)
        Slides
    • 15:50
      Break
    • OPENING 2
      slides
      • 6
        The future of the LHC programme and machine
        Speaker: Sergio Bertolucci (CERN)
        Slides
      • 7
        HEP experiments in Japan : The Next Generation
        The HEP experiment in Japan is now stepping into the next phase. The J-PARC, which is a newly-built high intensity proton synchrotron facility, started the operation recently. A new long-baseline neutrino experiment T2K is now at the commisioning stage utilizing the beam. In parallel, the upgrade of the KEKB/Belle, the new-stage B-factory experiment at KEK, is about to start. The accelerator will be upgraded to SuperKEKB whose luminosity is expected to be more than 50 time higher. The detector is also upgraded to Belle II to keep up with the increased rate. In this talk, a detailed review is given for these new experiments with some coverage of the readout and DAQ technologies.
        Speaker: Dr Ryosuke Itoh (KEK)
        Slides
      • 8
        ILC-CLIC
        The planned linear colliders - international linear collider (ILC) and compact linear collider (CLIC)- will provide electron-positron collisions in the TeV range. Due to the high energy of the passing electrons and positrons at the interaction point a large number of background particles not related to the collision are produced. Thus the detectors must identify and reject these background particles providing small spatial segmentation and precise particle arrival time identification. In order not to influence the particle trajectory and to provide precision measurements the amount of detector material and services need to be reduced to a minimum. Especially for CLIC, the acceleration scheme results in a bunch crossing timing structure posing a challenge to the detector and read-out electronics implementation. In the presentation the specifications and challenges of the detector and read-out electronics for linear colliders are discussed.
        Speaker: Alex Kluge (CERN)
        Slides
    • 18:30
      Welcome Drink
    • 9
      Executive Summary
      Paper
  • Tuesday, 22 September
    • Plenary Session 1 - Beam Condition Monitors and Machine-Experiment Interlocks
      • 10
        Experiment protection at the LHC and damage limits in LHC(b) silicon detectors
        A review is given of possible beam failure modes at the LHC and of the strategy adopted in the LHC experiments to protect the detectors against such events. Damage limits for the detectors are discussed and, in particular, some recent experimental tests concerning the LHCb silicon microstrip vertex detector are presented.
        Speaker: Massimiliano Ferro-Luzzi (CERN)
        Paper
        Slides
    • Parallel session A1 - ASICs
      Convener: Alessandro Marchioro (CERN)
      • 11
        About 10000 frames per second readout MAPS for the EUDET beam telescope
        Designed and manufactured in a commercial CMOS 0.35 μm Opto process for equipping the EUDET beam telescope, MIMOSA-26 is the first reticule size pixel sensor with digital output and integrated zero suppression. It features a matrix of pixels of 576 rows and 1152 columns covering an active area of ~224 mm2. A single point resolution, better than 4 μm, is expected with a pixel pitch of 18.4 μm. Its architecture allows a fast readout frequency of ~10 k frames/s. The workshop contribution will present, in details, the chip design, test and its major characterisation outcome.
        Speaker: Dr Christine HU-GUO (DRS-IPHC Strasbourg (IReS))
        Paper
        Slides
      • 12
        Front-End Electronics for Pixel Detector of the PANDA MVD.
        ToPix 2.0 is a prototype in a CMOS 0.13 μm technology of the front-end chip for the hybrid pixel sensors that will equip the Micro-Vertex Detector of the PANDA experiment at GSI. The Time over Threshold (ToT) approach has been employed to provide a high charge dynamic range (up to 100 fC) with a low power dissipation (15 μW/cell). In an area of by 100 μm×100 μm each cell incorporates the analog and digital electronics necessary to amplify the detector signal and to digitize the charge information. ToPix 2.0 includes 320 pixel readout cells organized in four columns and a simplified version of the end of column readout.
        Speaker: Thanushan Kugathasan (INFN – Sezione di Torino, Università di Torino)
        Paper
        Slides
    • Parallel session B1 - Systems, Installation and Commissioning
      Convener: Geoff Hall (Imperial College)
      • 13
        The Noise Performance of the CMS Detector
        The design of the CMS power distribution system plays a major role in the ultimate noise performance of detector, both from the perspective of internally generated noise and of noise coupling between subdetectors. Noise considerations in a detector power system depend strongly on the mechanical configuration of the detector and the cabling and grounding conventions used. This talk will review the commissioning history of CMS from the point of view of noise performance and interactions between detector subsystems. Particular emphasis is placed on the influence of the global mechanical design of CMS, as well as that of its subdetectors.
        Speaker: Dr Sergei Lusin (Fermilab)
        Slides
      • 14
        Commissioning of the DT electronics under magnetic field.
        After several months of completing the installation and commissioning of the CMS (Compact Muon Solenoid) DT (Drift Tube) electronics, the system has finally been operated under magnetic field during the so-called CRAFT (Cosmic Run at Four Tesla) exercise. Over 4 weeks, the full detector has been running continuosly under magnetic field and achieved to acquire up to 300 million cosmic muons. The performance of the trigger and data acquisition systems during this period has been very satisfactory and the main results concerning stability and reliability of the detector are presented and discussed.
        Speaker: Mrs Cristina Fernandez Bedoya (Cent.de Investigac.Energeticas Medioambientales y Tecnol. (CIEMAT))
        Paper
        Slides
    • 10:35
      Break
    • Parallel session A1 - ASICs
      Convener: Christophe de La Taille (LAL Orsay)
      • 15
        Advanced Pixel Architectures for Scientific Image Sensors
        We will present recent developments from two projects targeting advanced pixel architectures for scientific applications. Results will be reported from test structures demonstrating variants on a 4T pixel architecture. The variants include differences in pixel and diode size, the in-pixel source follower transistor size and the capacitance of the readout node to optimise for low noise and high dynamic range. Results will also be reported from TPAC, a complex pixel architecture, which has been manufactured with a special deep P-well process and on a high resistivity substrate for enhanced charge collection performance.
        Speaker: Ms Rebecca Coath (STFC - Rutherford Appleton Laboratory)
        Paper
        Slides
      • 16
        Performance of the ABCN-25 readout chip for ATLAS Inner Detector Upgrade
        We present the test results of the ABCN-25 front end chip implemented in CMOS 0.25um technology and optimized for the short, 2.5cm, silicon strips intended to be used in the upgrade of the ATLAS Inner Detector. We obtain the full functionality of the readout part, the expected performance of the analogue front-end and the operation of the power control circuits. The performance is evaluated in view of the minimization of the power consumption, as the upgrade detector may contain up to 70 millions channels. System tests with different power distribution schemes proposed for the future tracker detectors are possible with this chip. The ABCN-25 ASIC is now serving as the prototype readout chip in the developments of the modules and staves for the upgrade of the ATLAS Inner Detector.
        Speaker: Mr Francis Anghinolfi (CERN)
        Paper
        Slides
      • 17
        Reduction techniques of the back gate effect in the SOI Pixel Detector
        A pixel sensor in 0.2um Silicon-On-Insulator (SOI) CMOS technology, consisting of a thick sensor layer and a thin circuit layer with an insulating buried-oxide in a monolithic chip, has many advantages. However, it has been found that applied electric field in the sensor layer also affects transistors in the adjacent circuit layer. Thus, full depletion voltage cannot be applied. To overcome this, we performed TCAD simulation and added an additional p-well (buried p-well) in the SOI process. Simultaneously, we attempt vertical integration of two SOI chips by using a micro-bonding technique. Designs and preliminary results will be presented.
        Speaker: Dr Ryo Ichimiya (KEK)
        Paper
        Slides
      • 18
        Low noise, low power front end electronics for pixelized TFA sensors
        In this paper we present the preliminary experimental results obtained with 10 µm thick hydrogenated amorphous silicon sensors, deposited directly on top of integrated circuit optimized for tracking applications at linear collider experiments. The signal charges delivered by such a-Si:H n-i-p diode are small; about 37 e-/µm for a minimum ionizing particle, therefore a low noise, high gain and very low power front-end circuitry is of primary importance. The developed demonstrator chip comprises an array of 64 by 64 pixels laid out in 40 µm by 40 µm pitch designed in 250 nm CMOS technology.
        Speaker: Prof. Wladyslaw Dabrowski (Faculty of Physics and Applied Computer Science, AGH University of Science and Technology, Al. Mickiewicza 30, 30-059 Cracow, Poland)
        Paper
        Slides
    • Parallel session B1 - Systems, Installation and Commissioning
      Convener: Ken Wyllie (CERN)
      • 19
        Data acquisition system for a proton imaging apparatus
        New developments in the proton-therapy field for cancer treatments, leaded Italian physics researchers to realize a proton imaging apparatus consisting of a silicon microstrip tracker, to reconstruct the proton trajectories, and a calorimeter, to measure their residual energy. For clinical requirements, the detectors used and the data acquisition system should be able to sustain 1 MHz proton rate. The tracker read-out, using an ASICs, acquires the signals detector and sends data in parallel to an FPGA. The YAG:Ce calorimeter generates also the global trigger. The data acquisition system and the results obtained with a 60MeV proton beam are presented and discussed
        Speaker: Dr Valeria Sipala (Dipartimento di Fisica - Università degli Studi di Catania & INFN sez Catania)
        Paper
        Slides
      • 20
        BAO radio electronic system
        The description of the electronic chain for the BArionicOscillation project The BAO Radio project aims at mapping the H gas distribution in the universe using the 21 cm (1420 MHz) hyperfine transition of atomic hydrogen, up to red-shifts z ~ 1.5-2. The main goal of the project is to constrain the Dark Energy properties using the BAO (Baryon Acoustic Oscillation) cosmological probe, which can be considered as a "standard ruler". The large frequency range (0.5-1.5 GHz), large sky coverage (1/2 sky) and resolution (~ 10 arc'') are the main observational constraints which have driven the electronics. The electronics chain is installed for test at the second biggest radio-telescope in the word at Nancay (France) and foreseen to be installed at Pittsburgh (USA). Its architecture can be separated in 3 segments: antenna/RF amplifier, digitization/signal processing/transmission, acquisition by PC. The analog signal coming from the dipole is amplified by a warm LNA then sent to the RF board on a 50-ohm copper cable. The latter behaves as amplifier/mixer: analog signal is filtered and thanks to a 1.2GHz local oscillator split in four 250 MHz bands to match the Nyquist condition of the 500 MHz digitization. This way the analog signal can directly enter the ADC, avoiding an anti-aliasing filter at its input. Nevertheless the possibility to work in down-conversion mode is foreseen, taking advantage of the 1500 MHz analog input bandwidth. The card is a 4-channel VME/USB board. It embeds two 500-MHz ADC, two StGX FPGA and 5-Gbits/s optical drivers. The FPGA perform the FTT in streaming mode, pack data, serialize it and encode it in a 8b/10b protocol and then send it on a 5 Gbit optical link. The PC server house a PCIExpress board based on a Actel STRATIXII, a raid controller board wich is able to manage 8 sata2 hard disk of 160GByte. The FPGA integrate: 128kByte of memory, a controller of the data integrity and a PCIExpress 4x interface. With this architecture we reach 500MByte/s of data transfer to the ram of the PCI and 360MByte/s from the ram to the disk.
        Speaker: Mr Daniel Charlet (Laboratoire de l''Accelerateur Lineaire (LAL) (IN2P3) (LAL))
        Slides
      • 21
        Deep-sea data transfer at the KM3NeT neutrino telescope
        KM3NeT is a future cubic kilometre-scale neutrino telescope for the deep Mediterranean. Several hundred vertical detection lines, each containing up to 100 optical modules with photomultipliers will be anchored to a sea floor power and data transport network. Data acquisition will minimize offshore electronics, reducing difficult and expensive maintenance operations. No off-shore triggering or filtering combining signals from multiple optical modules is foreseen; all signals passing internal criteria (e.g. charge threshold) will be uploaded via a fibreoptic telecommunications cable at an overall data rate of~ 100Gb/s. Various options for front-end digitization and data transport, including colour multiplexing, are discussed
        Speaker: Dr Gregory Hallewell (Centre de Physique des Particules de Marseille)
        Slides
      • 22
        Commissioning and performance of the Preshower off-detector readout electronics in the CMS experiment
        The CMS Preshower is a fine grain detector that comprises 4288 silicon sensors, each containing 32 strips. The raw data are transferred from the detector to the counting room via 1208 optical fibres producing a total data flow of ~72GB/s. For their readout, 40 multi-FPGA 9U VME readout boards are used. This article is focused on the commissioning of the VME readout system using two tools: a custom connectivity test system based on FPGA embedded logic analyzers read out through JTAG; an FPGA-based system that emulates the data-traffic from the detector. Additionally, the performance of the VME readout system in the CMS experiment, including the 2009 CRAFT run (Cosmic ray at Four Tesla), is discussed.
        Speaker: Dr Paschalis Vichoudis (CERN)
        Paper
        Slides
      • 23
        In-situ performance of the CMS Preshower Detector
        The CMS Preshower detector, based on silicon strip sensors, was installed on the two endcaps of CMS in March/April 2009. First commissioning showed that of the 137000 electronics channels virtually all were fully operational. This report summarizes the electronics integration (on-detector) and in-situ performance in terms of noise (including common-mode pickup), channel-to-channel variations, gain uniformities etc. Comparisons are made between these measurements and those made during assembly and system-tests. First observations of in-situ cosmic-rays are expected during the Summer.
        Speaker: Dr Wojciech Bialas (CERN)
        Paper
        Slides
    • 13:05
      Lunch
    • Plenary Session 2 - Low Power Analog Design Techniques
      • 24
        Low Power Analog Design in Scaled CMOS Technologies
        The running CMOS technology scaling has a big impact in the design of analog circuits. Since scaled technologies offer big advantages to digital parts (reduce space, lower power consumption, etc...), complex mixed-signal systems are typically developed in the smallest minimum-gate-length technology. However these advantages for the digital part in a scaled technology correspond to a big penalty in the analog design. Typical problems are due to the lower output impedance, to the lower available output swing and to the lower distance from VDD to VTH (VDD scales faster than VTH). Analog designers have then to develop new solutions for achieving in scaled technologies the same performance previously achieved in "older" technologies. In this talk these problems will be addressed for the cases of basic building blocks. The discussion will then move to their effects on complex systems showing the possible solutions in 90nm/65nm.
        Speaker: Andrea Baschirotto (University of Milan-Bicocca)
        Slides
    • Parallel session A2 - ASICs
      Convener: Alessandro Marchioro (CERN)
      • 25
        Gossipo-3: a prototype of a Front-end Pixel Chip for Read-out of Micro-Pattern Gas Detectors.
        In a joint effort of Nikhef (Amsterdam) and University of Bonn, the Gossipo-3 IC is being developed. This circuit is a prototype of a full-reticle chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors. The chip is defined as a high granulated (55um) array in which every readout pixel is equipped with a high resolution TDC (1.6ns) covering dynamic range up to 100us. This feature allows for a high precision 3D track reconstruction originated by particles passing through the gas volume. The circuit is also optimized for low power consumption (100mW/cm^2) required to avoid the need for massive power transport and cooling systems in the construction of the detector. In the presentation the detector principle will be explained and various design aspects of the on-pixel circuits will be discussed.
        Speaker: Mr Vladimir Gromov (NIKHEF)
        Paper
        Slides
      • 26
        DIRAC v2: a DIgital Readout Asic for hadronic Calorimeter
        This mixed-signal circuit is a 64 channels readout R&D ASIC for Micro-Pattern Gaseous Detectors (Micromegas, Gas Electron Multiplier) or Resistive Plate Chambers. These detectors are foreseen as the active part of a digital hadronic calorimeter for a high energy physics experiment at the International Linear Collider. Physics requirements lead to a highly granular hadronic calorimeter with up to fifty millions channels with probably only hit information (digital calorimeter). The first version of this chip has been tested in beam last year on a detector, thus proving the feasibility of Micromegas with embedded digital readout.
        Speaker: Dr Renaud Gaglione (LAPP, Université de Savoie, CNRS/IN2P3)
        Paper
        Slides
      • 27
        HARDROC, Readout chip of the Digital Hadronic Calorimeter of ILC
        HARDROC (HAdronic Rpc Detector ReadOut Chip) is the very front end chip designed for the readout of the RPC or Micromegas foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider. The very fine granularity of the ILC hadronic calorimeters (1cm2 pads) implies a huge number of electronics channels (400 000 /m3) which is a new feature of “imaging” calorimetry. Moreover, for compactness, the chips must be embedded inside the detector making crucial the reduction of the power consumption to 10 µWatt per channel. This is achieved using power pulsing, made possible by the ILC bunch pattern (1 ms of acquisition data for 199 ms of dead time). HARDROC readout is a semi-digital readout with two or three thresholds (2 or 3 bits readout respectively in hardroc1 and hardroc2) which allows both good tracking and coarse energy measurement, and also integrates on chip data storage. The 64 channels of the 2nd prototype, HARDROC2, are made of: • Fast low impedance preamplifier with a variable gain over 8 bits per channel • A variable slow shaper (50-150ns) and Track and Hold to provide a multiplexed analog charge output up to 15pC. • 3 variable gain fast shapers followed by 3 low offset discriminators to autotrig down to 10 fC up to 10pC. The thresholds are loaded by 3 internal 10 bit- DACs and the 3 discri outputs are sent to a 3 inputs to 2 outputs encoder • A 128 deep digital memory to store the 2*64 encoded outputs of the 3 discriminators and bunch crossing identification coded over 24 bits counter. • Power pulsing and integration of a POD (Power On Digital) module for the 5MHz and 40 Mhz clocks management during the readout, to reach 10µW/channel The overall performance of HARDROC will be described with detailed measurements of all the characteristics. Hundreds of chips have indeed been produced and tested before being mounted on printed boards developed for the readout of large scale (1m2) RPC and Micromegas prototypes. These prototypes have been tested with cosmics and also in testbeam at CERN in 2008 and 2009 to evaluate the performance of different kinds of GRPCs and to validate the semi-digital electronics readout system in beam conditions.
        Speaker: Mrs Nathalie Seguin-Moreau (OMEGA/LAL ORSAY/IN2P3)
        Paper
        Slides
    • Parallel session B2a - Production, testing and reliability
      • 28
        Replacing full custom DAQ test system by COTS DAQ components on example of ATLAS SCT readout
        A test system developed for ABCN-25 for ATLAS Inner Detector Upgrade is presented. The system presented is based on commercial off the shelf DAQ components by NI and foreseen to aid in chip characterization and module/hybrid development complementing full custom VME based setups. The key differences from the point of software development are presented, together with guidelines for developing high performance LabVIEW code. Some real-world benchmarks will also be presented together with chip test results. The presented tests show good agreement of test results between the setups, as well as agreement with design specs of the chip.
        Speaker: Mr Michal Dwuznik (Faculty of Physics and Applied Computer Science AGH Univeristy of Science and Technology)
        Paper
        Slides
      • 29
        Integrated test environment for a part of the LHCb calorimeter
        An integrated test environment for the data acquisition electronics of the Scintillator Pad Detector (SPD) from the calorimeter of the LHCb experiment is presented. It allows to test separately every single board or to perform global system tests, while being able to emulate every part of the system and debug it. This environment is foreseen to test the production of spare electronics boards and help to the maintenance of the SPD electronics along the life of the detector. The heart of the system is an Altera Stratix II FPGA while the main board can be controlled over USB, Ethernet or WiFi.
        Speaker: Mr Carlos Abellan Beteta (Universidad de Barcelona-Unknown-Unknown)
        Paper
        Slides
      • 30
        Picosecond time measurement using ultra fast analog memories.
        The currently existing electronics dedicated to precise time measurement is mainly based on the use of constant fraction discriminators (CFD) associated with Time to Digital Converters (TDC). The time resolution measured on the most advanced ASICs based on CFDs is of the order of 30 ps rms. TDC architectures are usually based either on a voltage ramp started or stopped by the digital pulse, which offers an excellent precision (5 ps rms) but is limited by the large dead time, or on a coarse measurement performed by a digital counter associated with a fine measurement (interpolation) using Delay Line Loop, which exhibits a timing resolution of 25 ps, but only after a careful calibration. In the meantime, alternative methods based on digital treatment of the analogue sampled then digitized detector signal have been developed. Such methods permit achieving a timing resolution far better than the sampling frequency. Digitization systems have followed the progress of commercial ADCs, but the latter have prohibitory drawbacks as their huge output data rate and power consumption. Conversely, high speed analog memories now offer sampling rates far above 1GHz at low cost and with low power consumption. The new USB-WaveCatcher board has been designed to provide high performances over a short time window. It houses on a small surface two 12-bit 500-MHz-bandwidth digitizers sampling between 400 MS/s and 3.2 GS/s. It is based on the patented SAM chip, an analog circular memory of 256 cells per channel designed in a cheap pure CMOS 0.35µm technology and consuming only 300 mW. The board also offers a lot of functionalities. It houses a USB 12 Mbits/s interface permitting a dual-channel readout speed of 500 events/s. Power consumption is only 2.5 W which permits powering with the sole USB. In an embodiment of the board optimized for time measurement, a reproducible time precision of a few ps has been demonstrated. The USB-WaveCatcher can thus replace oscilloscopes for a much lower cost in most high-precision short-window applications. Moreover, it opens new doors into the domain of very high precision time measurements.
        Speaker: Mr Dominique Breton (Laboratoire de l'Accelerateur Lineaire (LAL/IN2P3/CNRS))
        Paper
        Slides
    • 16:15
      Late break
    • Parallel session A2 - ASICs
      Convener: Jorgen Christiansen (CERN)
      • 31
        Design of High Dynamic Range Digital to Analog Converters for Calibration of the CALICE readout electronics
        The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35µm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the amplifiers can be put into a standby mode reducing the power dissipation. The 12 bit DAC features an INL lower than 0.4 LSB at 5MHz, and dissipates less than 7mW. The 14 bit DAC is an improved version of the 12 bit design.
        Speaker: Mr Laurent Gallin-Martel (LPSC/IN2P3 Grenoble)
        Paper
        Slides
      • 32
        A SiGe ASIC Prototype for the ATLAS LAr Calorimeter Front-End Upgrade
        We have designed and fabricated a very low noise preamplifier and shaper to replace the existing ATLAS Liquid Argon readout for use at Large Hadron Collider upgrade (SLHC). IBM’s 8WL 130nm SiGe process was chosen for its radiation tolerance, low noise bipolar NPN devices, wide voltage range and potential for use in other LHC detector subsystems. The required dynamic range of 15 bits is accomplished with a single stage, low noise, wide dynamic range preamp followed by a dual range shaper. The low noise of the preamp is made possible by the low base spreading resistance of Silicon Germanium NPN bipolar transistors. The relatively high voltage rating of the NPN transistors is exploited to allow a gain of 650V/A in the preamplifier, which eases the input voltage noise requirement of the shaper. Each shaper stage is designed as a cascaded differential op amp doublet with a common mode operating point regulated by an internal feedback loop. Preliminary measurement of the fabricated circuits indicates their performance is consistent with the design specifications.
        Speaker: Mitchell Franck Newcomer (Departm.of Physics & Astronomy)
        Paper
        Slides
    • Parallel session B2b - Radiation tolerant components and systems
      • 33
        Measurement of radiation damage of 130nm hybrid pixel detector readout chips
        We present the first measurements of the performance of the Medipix3 hybrid pixel readout chip after exposure to significant x-ray flux. Specifically the changes in performance of the mixed mode pixel architecture, the digital periphery, digital to analogue converters and the e-fuse technology were characterised. A high intensity, calibrated x-ray source was used to incrementally irradiate the separate regions of the detector whilst it was powered. This is the first total ionizing dose study of a large area pixel detector fabricated using the 130nm CMOS technology.
        Speaker: Dr Richard Plackett (CERN)
        Paper
        Slides
      • 34
        Radiation tests on the complete system of the instrumentation of the LHC Cryogenics at the CERN Neutrinos to Gran Sasso (CNGS) test facility
        There are more than 6000 electronic cards for the instrumentation of the LHC cryogenics, housed in crates and distributed around the 27km tunnel. Cards and crates will be exposed to a complex radiation field during the 10y of LHC operation. COTS and rad-tol ASIC have been selected and individually qualified during the design phase of the cards. The test setup and the acquired data presented in this paper target the qualitative assessment of the compliance with the LHC radiation environment of an assembled system. It is carried out at the CNGS test facility which provides exposure to LHC-like radiation field.
        Speaker: Ms Evangelina GOUSIOU (CERN)
        Paper
        Slides
      • 35
        Development of new readout electronics for the ATLAS LAr calorimeter at the sLHC
        The ATLAS Liquid Argon (LAr) calorimeter consists of 182,486 detector cells whose signals need to be read out, digitized and processed, in order to provide signal timing and the energy deposited in each detector element. The current readout electronics is not designed to sustain the ten times higher radiation levels expected at sLHC in the years ≥2017, and will be replaced by new electronics with a completely different readout scheme. The future on-detector electronics is planned to send out all data continuously at each bunch crossing, as opposed to the current system which only transfers data at a trigger-accept signal. Multiple high-speed and radiation-resistant optical links will transmit 100 Gbps per front-end board, each covering 128 readout channels. The off-detector processing units will not only process the data in real-time and provide digital data buffering, but will also implement trigger algorithms. An overview about the various components necessary to develop such a complex system will be given. The current R&D activities and architectural studies of the LAr Calorimeter group will be presented, in particular the on-going design of the mixed-signal and radiation hard front-end ASICs, the Silicon-on-Saphire (SOS) based optical-link, the high-speed off-detector FPGA based processing units and the power supply distribution scheme.
        Speaker: Arno Straessner (IKTP, TU Dresden)
        Paper
        Slides
    • MUG
      • 36
        Access to ASIC Design Tools and Foundry Services at CERN for SLHC
        Speaker: Kostas Kloukinas (CERN)
        Slides
      • 37
        Mixed-Signal Challenges and Solutions for advanced process nodes
        Speaker: Bruno Dutrey (Cadence Design Systems)
        Slides
      • 38
        Digital Block Implementation Methodology for a 130nm process
        Speaker: Sandro Bonacini (CERN)
        Slides
      • 39
        Discussion
        Speaker: Kostas Kloukinas (CERN)
  • Wednesday, 23 September
    • Plenary Session 3 - Buses and boards, making the right choice
      • 40
        Buses and Boards
        From motherboard to backplane to blade based computer systems, the choices are numerous. This session will cover the markets and trends within those markets that are impacting decisions made by board suppliers. Discussion will focus on the various form factors, the development and evolution of industry standards, and the consortia that support and develop these standards, including VITA, PICMG, and others. The presentation will conclude with suggestions for choosing the right form factor for your application
        Speaker: Jerry Gipper (Embedify LLC)
        Paper
        Slides
    • Parallel Session A3 - Trigger
      Convener: Wesley Smith (University of Wisconsin)
      • 41
        Integrated Trigger and Data Acquisition system for the NA62 experiment at CERN
        The TDC based integrated trigger and data acquisition system of the NA62 experiment at CERN will be presented. The system architecture, the trigger algorithm and its implementation in commercial high performance FPGAs will be described. The results of test and characterization of the custom components as well as those of extensive field tests performed on a system prototype handling up to 512 input channels will be discussed.
        Speaker: Gianmaria Collazuol (INFN Sezione di Pisa (INFN))
        Paper
        Slides
      • 42
        A digital calorimetric trigger for the COMPASS experiment at CERN
        In order to provide a trigger for the Primakoff reaction, in 2009, the trigger system of the COMPASS experiment at CERN will be extend by an electromagnetic calorimeter trigger. Since it was decided to gain from various benefits of digital data processing, a FPGA based implementation of the trigger, running on the front-end electronics, which are used for data acquisition at the same time, is foreseen. This, however, includes further modification of the trigger system to combine the digital calorimeter trigger, with its higher latency, and the analogue trigger signals, which will although make use of digital data processing.
        Speaker: Mr Markus Krämer (Technische Universität München)
        Paper
        Slides
    • Parallel Session B3 - Packaging and Interconnects
      Convener: Ray Yarema (FNAL)
      • 43
        Construction and Performance of a Double-Sided Silicon Detector Module using the Origami Concept
        The APV25 front-end chip with short shaping time will be used in the Super-Belle Silicon Vertex Detector (SVD) in order to achive low occupancy. Since fast amplifiers are more susceptible to noise caused by their capacitive input load, they have to be placed as close to the sensor as possible. On the other hand, material budget inside the active volume has to be kept low in order to reduce multiple scattering. We currently construct a low mass sensor module with double-sided readout, where thinned APV25 chips are placed on a single flexible circuit glued onto one side of the sensor. The interconnection to the other side is done by Kapton fanouts, which are wrapped around the edge of the sensor.
        Speaker: Mr Christian Irmler (HEPHY Vienna)
        Paper
        Slides
      • 44
        Application of a new interconnection technology for the ATLAS pixel upgrade at SLHC
        We present an R&D activity aiming towards a new detector concept in the framework of the ATLAS pixel detector upgrade exploiting vertical integration technologies developed at the Fraunhofer Institute IZM-Munich. A new Solid-Liquid-InterDiffusion technique is investigated as an alternative to the bump-bonding process. We also investigate the extraction of the signals from the back of the electronic chip through Inter-Chip-Vias to achieve a higher fraction of active area with respect to the present pixel module design. We will present the layout and the first results obtained with a production of test-structures designed to investigate the SLID interconnection efficiency as a function of different parameters, i.e. the pixel size and pitch, and the planarity of the underlying layers.
        Speaker: Dr Anna Macchiolo (Max-Planck-Institut fuer Physik)
        Paper
        Slides
    • 10:35
      Break
    • Parallel Session A3 - Trigger
      Convener: Emilio Petrolo (CERN)
      • 45
        LHCb Level 0 Decision Unit
        The Level 0 Decision Unit (L0DU) is one of the main components of the first trigger level of the LHCb experiment. This 16 layers custom board receives data from the calorimeter, muon and pile-up sub-triggers and computes the level 0 decision, reducing the rate from 40MHz to 1MHz. The processing is implemented in FPGA using a 40MHz synchronous pipelined architecture. The L0DU algorithm is fully configured via the Experiment Control System without any firmware reprogramming. An overall L0DU latency of less than 450ns has been achieved. The board was installed in the experimental area in April 2007. It has played a major role in the commissioning of the experiment.
        Speaker: Dr Hervé Chanal (LPC Clermont-Ferrand)
        Paper
        Slides
      • 46
        PERFORMANCE OF THE CMS REGIONAL CALORIMETER TRIGGER
        The CMS Regional Calorimeter Trigger (RCT) receives 8 bit energies and a data quality bit from the HCAL and ECAL Trigger Primitive Generators (TPGs) and sends it to the Global Calorimeter Trigger (GCT) after processing. The RCT hardware consists of 1 clock distribution crate and 18 double-sided crates containing custom boards, ASICs, and backplanes. The electronics for the RCT have been fully installed since 2007. The RCT has been fully integrated into the CMS Level-1 Trigger chain. Regular runs, triggering on cosmic rays, prepare the CMS detector for the restart of the LHC. During this running, the RCT control is handled centrally by CMS Run Control and Monitor System communicating with the Trigger Supervisor. Online Data Quality Monitoring (DQM) evaluates the performance of the RCT during these runs. Offline DQM allows more detailed studies, including trigger efficiencies. These and other results from cosmic-ray data taking with the RCT will be presented.
        Speaker: Mrs Pamela Renee Klabbers (University of Wisconsin-Madison)
        Paper
        Slides
      • 47
        Analogue Input Calibration of the ATLAS Level-1 Calorimeter Trigger
        The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system using custom electronics which identifies, within a fixed latency of 2.5 us, highly energetic objects resulting from LHC collisions. It is composed of three main sub-systems. The PreProcessor system first conditions and digitises approximately 7200 pre-summed analogue calorimeter signals at the bunch-crossing rate of 40 MHz, and identifies the specific bunch-crossing of the interaction using a digital filtering technique. Pedestal subtraction and noise suppression applied, and final calibrated digitised transverse energies are transmitted in parallel to the two subsequent processor systems. Several channel-dependent parameters require setting in the PreProcessor system to provide these digital signals, aligned in time and properly calibrated. The different techniques which are used to derive these parameters are described, along with the quality tests of the analogue input signals and the status of the energy calibration.
        Speaker: John Morris (Queen Mary University of London)
        Paper
        Slides
      • 48
        Precise Timing Adjustment for the ATLAS Level1 Endcap Muon Trigger System
        The ATLAS level1 endcap muon trigger system consists of about 4000 Thin Gap Chambers (TGC) with 320,000 input electronics channels in order to find level1 trigger candidates for muons in both endcap regions. We had already adjusted channel-to-channel timing difference in overall TGC system with 1.2ns level, and found its consistency with the observation of beam halo events in the first proton circulation of LHC in September 2008. After that we have found some more correction factors to be incorporated with and eventually achieved timing adjustment in 0.9ns precision. In this presentation we also discuss an effective strategy for a parameter that can be adjusted using colliding beams.
        Speaker: Mr Yu Suzuki (KEK)
        Paper
        Slides
      • 49
        Framework for Testing and Operation of the ATLAS Level-1 MUCTPI and CTP
        The ATLAS Level-1 Muon to Central Trigger Processor Interface (MUCTPI) receives information on muon candidates from the muon trigger sectors and sends multiplicity values to the Central Trigger Processor (CTP). The CTP receives the multiplicity values from the MUCTPI and combines them with information from the calorimeter trigger and other triggers of the experiment and makes the final Level-1 decision. The MUCTPI and CTP are housed in two 9U VME64x crates and are made of eight different types of custom designed modules. This paper will present the framework which is used for debugging, commissioning and operation of all modules of the MUCTPI and CTP. Testing of the modules has been considered right from design. Most types of modules contain diagnostic memories at the input of the module which can be used to capture incoming data or to inject data into the module. Testing of the modules can be achieved by capturing data at input of a down-stream module, by reading out data from a monitoring buffer at output, or by reading out monitoring counters. A layered software framework using C++ has been developed for configuring and controlling all modules and for testing them independently or grouped into complete sub-systems. The lowest level uses the ATLAS VME library and driver. At the next highest level, a compiler translates a description of the VME registers from XML to C++ code. This code together with existing code for some components, e.g. HPTDC, DELAY25, and JTAG, is combined to the low-level library of the module. A menu program provides access to all methods of the module low-level library. Generators create data for the test memories. Simulators calculate the expected results. Generators, simulators and the low-level library are combined to a suite of test programs which cover the full functionality of the MUCTPI and CTP. The low-level library is also used by the run control and monitoring programs which integrates the sub-systems into the ATLAS experiment control and monitoring framework.
        Speaker: Mr Ralf Spiwoks (CERN)
        Paper
        Slides
    • Parallel Session B3 - Packaging and Interconnects
      Convener: Jorgen Christiansen (CERN)
      • 50
        Prototype flex hybrid and module designs for the ATLAS Inner Detector Upgrade utilising the ABCN-25 readout chip and Hamamatsu large area Silicon sensors.
        We will present the development of prototype flex hybrids and modules for the short strip layers of the ATLAS inner detector upgrade. The hybrid utilises the ABCN-25 front end readout chip, which has been optimised for the short 2.5cm strip sensor topology. The design and production choices for a high yield, low cost reliable device will be discussed. Preliminary results from the first prototype hybrids and the first short strip module demonstrator, featuring a 10cm x 10cm Hamamatsu sensor with 4 x 1280 strips read out by 40 readout chips, will be presented. We will also discuss the future plans for the development of a mass-producible, non-rigidised flex circuit that can be glued directly onto the silicon sensor for integration onto a stave structure.
        Speaker: Mr Ashley Greenall (Department of Physics)
        Slides
      • 51
        The First Vertically Integrated MPW Run for HEP
        In 2008 a consortium of 15 international institutions was formed to pursue the development of 3D integrated circuits at a commercial foundry. The first MPW run from the consortium was submitted to Tezzaron. Wafers were fabricated at Chartered Semiconductor in the 130 nm process. These wafers were then assembled by Tezzaron into vertically integrated circuits. More than fifteen designs were submitted. Designs include custom analog and digital circuits for particle detection in ATLAS, CMS, ILC and other experiments. Issues related to the submission of the MPW run and initial results will be presented.
        Speaker: Mr Ray Yarema (FNAL)
        Slides
      • 52
        3D electronics for hybrid pixel detectors
        Facing the future challenges of hybrid pixel vertex detectors is foreseen to be done by microelectronic technology shrinking. However, this straightforward approach has some disadvantages in term of performances and cost. Based on a previous prototype of the future ATLAS pixel read-out chip FE-I4, this paper presents design and test of a hybrid pixel read-out chip using 3 dimensional electronics technologies which enable to split pixel functionalities into two separate levels.
        Speaker: Mrs Stéphanie Godiot (CPPM)
        Paper
        Slides
      • 53
        Thin, Fully Depleted Monolithic Active Pixel Sensor with Binary Readout based on 3D Integration of Heterogeneous CMOS Layers
        On the way towards fast, radiation tolerant and ultra thin CMOS sensors, we propose new generation of devices based on commercial availability of vertical integration of several CMOS wafers (3D Electronics). The proposed prototype device is a 245x245 pixel array with a pitch of 20 µm, In the first silicon layer charge sensing diode and the input buffer amplifiers are integrated, using 0.6 µm CMOS on high resistivity epitaxial wafers. Following stage of processing electronics (charge integration, time invariant shaping and signal discrimination), are placed in the second silicon layer (0.13 micron CMOS). Third layer (same 0.13 CMOS) is used for implementation of fast, digital (binary) readout.
        Speaker: Mr Wojciech Dulinski (IPHC, Strasbourg)
        Slides
    • 13:05
      Lunch
    • Plenary Session 4 - Low Noise Design for Large Detectors
      • 54
        Low Noise Design for Large Detectors
        Low common mode noise design methods for small instruments such as oscilloscopes are well known. Extending these ideas to very large systems such as detectors at the Large Hadron Collider is often not very obvious. This talk will describes methods for developing large detector designs and provide some examples of successful designs using these ideas. It will also describe some common design mistakes and how to avoid them.
        Speaker: Marvin Johnson (Fermi National Accelerator Laboratory (FNAL))
        Paper
        Slides
    • Parallel Session B4 - Power, Grounding and Shielding
      Convener: Philippe Farthouat (CERN)
      • 55
        Progress on DC-DC converters for SiTracker for SLHC
        Previous tests have shown that Enpirion EN5360, a 6 amp device is capable of taking sLHC radiation dosage but the input voltage is limited to a maximum of 5.5V. But from a systems point of view it is essential to have a factor of 10 in input/out voltage ratio in single stage i.e. maximum input voltage be >12 Volts. The silicon foundry that made this device can now make 12 V FETS on the same 0.25 µm process with good irradiation results that are reported. Plug in power cards with x10 voltage ratio are being developed for testing the hybrids with ABCN chips, these have air coils but using commercial chips that may not be radiation hard but help in system noise and performance testing.
        Speaker: Dr Satish Dhawan (Yale University)
        Paper
        Slides
      • 56
        ASIC buck converter prototypes for LHC upgrades
        In the context of a new power distribution scheme for SHLC tracker based on switching DC/DC converter, we are developing a custom converter able to work in the high radiation and high magnetic field environment of the experiments. Two new ASIC prototypes, in two different technologies, have been designed and manufactured. Design techniques, functional and radiation tests of the prototypes will be discussed.
        Speaker: Mr Stefano Michelis (CERN)
        Paper
        Slides
    • Parallel session A4 - Trigger
      Convener: Emilio Petrolo (INFN Roma)
      • 57
        Feasibility studies of a Level-1 Tracking Trigger for ATLAS
        The existing ATLAS Level-1 trigger system is seriously challenged at the SLHC's higher luminosity. A hardware tracking trigger might be needed, but requires a detailed understanding of the detector. Simulation of high pile-up events, with various data-reduction techniques applied, will be described. Two scenarios are envisaged: (a) regional readout - calorimeter and muon triggers are used to identify portions of the tracker; and (b) track-stub finding using special trigger layers. A proposed hardware system, including data reduction on the front-end ASICs, readout within a super-module and integrating regional triggering into all levels of the readout system will be discussed.
        Speaker: Matt Warren (UCL)
        Paper
        Slides
      • 58
        Design of a module providing trigger information from the CMS Tracker at SLHC
        The CMS experiment is planning a major upgrade of its tracking system to adapt to an expected increase in luminosity of the LHC accelerator to 1035 cm-2.s-1. The CMS Tracker will then have to cope with several hundred interactions per bunch crossing and fluxes of thousands of charged particles emerging from collisions. CMS requires tracker data to contribute to the first level trigger, which must maintain the present 100kHz rate for compatibility with existing sub-detector systems while increasing the trigger decision latency by only a few µs. It must be achieved if possible without significantly compromising the tracking performance which is very sensitive to the material budget. A key part of a system to achieve this will be the design of a suitable module to generate trigger primitives. A module which might allow to provide suitable track trigger primitives is described and implications for the system are discussed.
        Speaker: Prof. Geoff Hall (Imperial College London)
        Paper
        ppt slides
        Slides
    • 15:50
      Break
    • Parallel Session B4 - Power, Grounding and Shielding
      Convener: Allain Godinec (CERN)
      • 59
        Experimental studies towards a DC-DC conversion powering scheme for the CMS silicon strip tracker at SLHC
        The distribution of power to the CMS tracker upgrade at SLHC is challenging, as the power consumption is expected to be similar as or higher than today, while the operating voltage will decrease and the cables must remain the same. The CMS tracker has adopted parallel powering with DC-DC conversion as baseline solution to the powering problem. The current status of the implementation of DC-DC converters into the CMS strip tracker at SLHC phase-2 will be presented. The presentation will include measurements with current tracker structures and custom converter PCBs, studies of the noise coupling and detector susceptibility (e.g. with the Bulk Current Injection method), and simulations of the effect of various powering schemes on the tracker material budget.
        Speaker: Dr Katja Klein (I. Physikalisches Institut (B))
        Paper
        Slides
      • 60
        System Integration Issues of DC to DC converters in the sLHC Trackers
        The upgrade of the trackers at the sLHC experiments requires implementing new powering schemes that will provide an increased power density with reduced losses and material budget. A scheme based on buck and switched capacitors DC to DC converters has been proposed as an optimal solution. The buck converter is based on a power ASIC, connected to a custom made air core inductor. The arrangement of the parts and the board layout of the power module are designed to minimize the emissions of EMI in a compact volume, enabling its integration on the tracker modules and staves.
        Speaker: Mr Georges Blanchot (CERN)
        Paper
        Slides
      • 61
        Performance and comparison of custom serial powering regulators and architectures for SLHC silicon trackers
        Serial powering is an elegant solution to power the SLHC inner trackers with a minimum volume of cables. So far R&D on serial powering for silicon strip modules was based on discrete commercial electronics. With the delivery of the first iteration of the ABCN-25 readout chip and the SPi serial powering interface chip, custom elements of shunt regulators and transistors became available. The combination of ABCN-25 and SPi can be used to implement three complementary serial powering architectures. The performance and features of the three architectures obtained with 20 chip and 10 chip ABCN-25 hybrids will be presented.
        Speaker: Tomas Tic (RAL/ASCR)
        Paper
        Slides
      • 62
        KM3NeT Power and Submarine Cable Systems for the kilometre cube Neutrino Telescope
        The KM3NeT EU-funded consortium, pursuing a cubic kilometre scale neutrino telescope in the Mediterranean sea, is developing technical solutions for the construction of this challenging project, to be realized several kilometres below the sea level. In this framework a proposed DC/DC power system has been designed, maximizing reliability and minimizing difficulties and expensive underwater activities. The power conversion, delivery, transmission and distribution network will be presented with particular attention to: main electro-optical cable, on shore and deep sea power conversion, subsea distribution network, connection systems, installation and maintenance issue.
        Speaker: Mr Mario Sedita (INFN-LNS)
        Paper
        Slides
    • Parallel session A4 - Trigger
      Convener: Wesley Smith (University of Wisconsin)
      • 63
        Trigger Platforms for CMS at the SLHC
        CERN has made public a comprehensive plan for upgrading the LHC accelerator to provide increased luminosity commonly referred to as SuperLHC (SLHC). The plan envisages two phases of upgrades during which the LHC luminosity increases gradually to reach 6-7×1034 cm-2sec-1. Over the past year CMS has responded with a series of workshops and studies which have defined the roadmap for upgrading the experiment to cope with the SLHC environment. Increased luminosity will result in increased backgrounds and challenges for CMS and a major part of the CMS upgrade plan is a new Level-1 trigger system which will be able to cope with high background environment at the SLHC. Two major CMS milestones will define the evolution of the CMS trigger upgrades: The change of the Hadronic Calorimeter electronics during phase-I and the introduction of the track trigger during phase-II. This paper outlines different alternative designs for a new trigger system. In particular, it looks at different algorithms and how they might be best implemented on different hardware platforms and the consequences for cost, latency, complexity and flexibility. The hardware platforms used to evaluate the performance of the algorithms are based on Xilinx V5 FPGAs.
        Speaker: Dr Gregory Michiel Iles (Imperial College)
        Paper
        Slides
      • 64
        Design Considerations for an Upgraded Track-Finding Processor in the Level-1 Endcap Muon Trigger of CMS for SLHC Operations
        D. Acosta, M. Fisher, I. Furic, J. Gartner, G.P. Di Giovanni, K. Kotov, A. Madorsky, D. Wang University of Florida/Physics, POB 118440, Gainesville, FL, USA, 32611 B. P. Padley, M. Matveev Rice University, Houston, Texas The conceptual design for a Level-1 muon track-finder trigger for the CMS endcap muon system is proposed that can accommodate the increased particle occupancy and system constraints of the proposed SLHC accelerator upgrade and the CMS detector upgrades. A brief review of the architecture of the current track-finder for LHC trigger operation is given, with potential bottlenecks indicated for SLHC operation. The upgraded track-finding processors described here would receive as many as two track segments detected from every cathode strip chamber comprising the endcap muon system, up to a total of 18 per 60° azimuthal sector. This would dramatically improve the efficiency of the track reconstruction in a high occupancy environment over the current design, since some of the track segments are filtered out in order to reduce transmission bandwidth and track processing logic. However, such an improvement would require significantly higher bandwidth and logic resources over the current design. We propose to use fastest available serial links, running asynchronously to the machine clock. Another enhancement critical for the overall Level-1 trigger capability for physics studies in phase 2 of the SLHC is to include the inner silicon tracking systems into the design of the Level-1 trigger. This requires matching muons identified in the endcap muon system and matching them to hits in the inner tracking system and refining the momentum measurement to improved precision for better rate reduction capabilities. Some preliminary ideas on the precision of information available from the endcap track-finder trigger will be presented along with possible algorithms for the matching.
        Speaker: Alexander Madorsky (University of Florida)
        Paper
        Slides
      • 65
        The GCT μTCA Matrix Card and its Applications
        The Matrix card is the first in what is expected to be a series of xTCA cards produced for a variety of projects at CERN, Trieste and LANL. Developed as a joint collaboration between colleagues at Princeton, Imperial College, LANL and CERN, the device comprises the latest generation of readily-available Xilinx FPGAs, crosspoint-switch technology and optical links in a 3U form factor. In this presentation we will discuss the development and test results of the Matrix card, followed by some of the tasks to which it is being applied.
        Speaker: Dr John Jones (Princeton University)
        Paper
        Slides
    • Power WG
      • 66
        SPI test results
        Speaker: Richard Philip Holt (Rutherford Appleton Laboratory)
        Slides
      • 67
        Irradiation results of technologies for a custom DCDC converter
        Speaker: Federico Faccio (CERN)
        Slides
      • 68
        EMC issues for CMS Tracker Upgrade
        Speaker: Fernando Arteche (Instituto Tecnológico de Aragón)
        Slides
      • 69
        Roadmap for serial powering
        Speaker: Marc Weber (Rutherford Appleton Laboratory)
        Slides
      • 70
        Roadmap for DC-DC
        Speaker: Federico Faccio (CERN)
        Slides
      • 71
        Discussion
    • 19:30
      Committe Meeting and Dinner
  • Thursday, 24 September
    • Plenary Session 5 - Key technologies for present and future optical networks
      • 72
        Key technologies for present and future optical networks
        In less than forty years, optical fiber has become omnipresent to convey high volumes of information over long distances for any segment of transport network. Short reach access networks are now boosted by the advent of 10Gigabit Ethernet standards, Fiber-To-The-Home and Passive Optical Networks technologies. Longer reach (from a few hundreds up to a few thousands of kilometers), terrestrial metropolitan and backbone networks have become translucent, based on the ability of lightpaths to traverse some Wavelength-Selective-Switch-based nodes without optoelectronic processing while being redirected depending on their wavelength; besides, those wavelength-multiplexed networks are about to become dynamically reconfigurable and very soon to transport capacities as high as 10 Terabit/s on a single fiber, using up to 100Gigabit/s optoelectronic transponders most likely based on Coherent Detection assisted by Digital Signal Processing. Eventually, submarine systems are expected to propose multi-terabit/s capacities over transoceanic distances. Such evolutions all aim at coping with the ever-increasing demand while lowering the cost and consumption of a transported bit. This paper draws an overview of the most recent evolutions and prospects for optical networks and the key associated technologies
        Speaker: Dr Jean-Christophe Antona (Alcatel-Lucent)
        Slides
    • Parallel Session A5 - ASICS
      • 73
        Smart Analogue Sampler for the Optical Module of a Cherenkov Neutrino Detector
        A transient waveform sampler/recorder IC has been developed and realized in AMS C35 technology to be used in the front-end of a neutrino detector. It is based around a switched capacitors array unit sampling its voltage inputs at 200MHz external clock rate and transferring them at its outputs at 1/10th of the sampling rate. This unit is replicated inside the ASIC providing 4 independent analogue sampling queues for signal transients up to 32 x 5ns and a fifth unit storing transients up to 128 x 5 ns. A micro-pipelined unit, based on Muller C-gates, controls the 5 independent samplers.
        Speaker: Luigi Caponetto (INFN/CNRS)
        Paper
        Slides
      • 74
        PARISROC, a photomultiplier array integrated readout chip
        PARISROC is a complete read out chip, in AMS SiGe 0.35μm technology [1],for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by French national agency for research (ANR) and called PMm2:“Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles” [2] (ref.ANR-06-BLAN-0186). The ASIC integrates 16 independent channels with variable gain and provides charge and time measurement by a 12-bit ADC and a 24-bits Counter.
        Speaker: Ms Selma Conforti Di Lorenzo (OMEGA/LAL/IN2P3/CNRS)
        Paper
        Slides
    • Parallel Session B5 - Optoelectronics and Links
      Convener: Francois Vasey (CERN)
      • 75
        Radiation Hardness of Graded-index Optical Fibre in Sub-Zero Temperature Environments
        Optical fibres experience significant differences in Radiation induced absorption (RIA) depending upon the temperature environment. At the LHC upgrade there are plans in some cases to mount optical fibres on or near to cold surfaces at sub-zero temperatures. Consequently a programme of characterization of optical fibre's RIA in cold environments is essential for identification of acceptable components and qualification of the final data links. We report temperature dependent radiation induced absorption from cold tests of optical fibres which are candidates for a future high energy physics detector. The optical fibre was exposed to ionizing radiation at -20 deg. C.
        Speaker: Dr B. Todd Huffman (Oxford University)
        Paper
        Slides
      • 76
        STUDY OF RADIATION HARDNESS OF PIN AND VCSEL ARRAYS
        We study the radiation hardness of 850 nm PIN/VCSEL arrays for possible deployment in the detector optical readouts for the LHC luminosity upgrades. In 2008, we irradiated two devices from several vendors to the radiation doses expected for the ATLAS silicon trackers. This leads to the identification of the best arrays from two vendors for possible deployment in a new ATLAS pixel-detector for the first phase of the luminosity upgrade. In 2009, we will irradiate a large sample of these arrays, together with some new devices available, to verify the radiation hardness. We will present the results from the irradiations.
        Speaker: Prof. K.K. Gan (The Ohio State University)
        Paper
        Slides
    • 10:35
      Break
    • Parallel Session A5 - ASICS
      • 77
        The 8 bits 100 MS/s pipe line ADC for the INNOTEP project
        This paper describes the Analog to Digital Converter developed for the front end electronic of the IN2P3 INNOTEP project by the “pole microelectronique Rhone-Auvergne”. (Collaboration LPC Clermont-Ferrand and IPNL Lyon). This ADC is a 4 stages, 2.5 bits per stage pipe line, with open loops track and holds and amplifiers. It runs at 100MSamples/s and has 8 bits of resolution. The stages used two lines, the gain line, and the comparison line which runs in current. The main idea of this current line is to make a first step toward current structure and 130nm technology. Currently, this ADC is designed with a 0,35µm SiGe technology.
        Speaker: Mr Sebastien Crampon (LPC Clermont Ferrand)
        Paper
        Slides
      • 78
        SuperNemo Absolute Time Stamper, a high resolution and large dynamic range TDC for SuperNemo experiment
        The SNATS chip is designed to provide both a high resolution of 70ps RMS and a large dynamic range of 53 bits. The architecture is based on the association of 32 cell delay locked loops and of a 48-bit digital counter which are synchronized to a 160 MHz external clock. A 16 channel prototype has been designed in AMS 0.35 µm CMOS technology and its main performances are a Differential Non Linearity of about 0.2 LSB and an Integral Non Linearity about 1.3 LSB. The circuit uses 12.7 mm2 of silicon area and is packaged in a 100-pin ceramic CQFP.
        Speaker: Mrs Vanessa Tocut (CNRS/IN2P3/LAL-ORSAY)
        Slides
      • 79
        A latchup topology to investigate novel particle detectors
        Here is described a novel approach to detect particles by means of a solid-state device susceptible to latchup-like effects. The stimulated ignition of latchup effects caused by external radiation has so far proven to be a hidden hazard. Here this is proposed as a powerful means of achieving the precise detection and positioning of a broad range of ionising particles. The cell can be constructed using state-of-the-art CMOS technologies. Thus, whenever this structure ignites upon charge detection, whatever its origin, a latchup condition is stated and this is a starting point for future pixel device designs.
        Speaker: Mr Alessandro Gabrielli (CERN EP-MIC - Physics Department & INFN Bologna)
        Paper
        Slides
      • 80
        A 5 Gb/s Radiation Tolerant Laser Driver in 0.13 um CMOS technology
        A laser driver for data transmission at 5 Gb/s has been developed as a part of the GigaBit Transceiver (GBT) project. The GigaBit Laser Driver (GBLD) targets High Energy Physics (HEP) applications for which radiation tolerance is mandatory. The GBLD ASIC can drive both VCSELs and some types of edge emitting lasers. It is essentially composed of two drivers capable of sinking up to 12 mA each from the load at a maximum data rate of 5 Gb/s, and of a current sink for the laser bias current. The laser driver also include pre-emphasis and duty cycle control capabilities.
        Speaker: Giovanni Mazza (INFN sezione di Torino, Italy)
        Paper
        Slides
      • 81
        The GBTIA, a 5 Gbit/s radiation-hard optical receiver for the SLHC upgrades
        This paper presents a 4.8 Gbit/s optical receiver designed in a 0.13 µm CMOS process as part of the GBT project. The receiver consists of a transimpedance amplifier (TIA) and a limiting amplifier. A differential cascode structure with inductive peaking is adopted for the TIA to achieve high gain, high bandwidth and low input referred noise. Experimental results at room temperature show an open eye diagram at 4.8 Gbit/s with rise time < 40 ps, a bandwidth of 4 GHz, and a sensitivity of < -16 dBm for a BER of 10-12. The total chip power consumption is < 120 mW.
        Speaker: Mr Mohsine Menouni (CPPM, Aix-Marseille Université, CNRS/IN2P3, Marseille, France)
        Paper
        Slides
    • Parallel Session B5 - Optoelectronics and Links
      Convener: Thijs Wijnands (CERN)
      • 82
        The GBT project
        The GigaBit Transceiver (GBT) architecture and transmission protocol has been proposed for data transmission in the physics experiments of the future upgrade of the LHC accelerator, the SLHC. Due to the high beam luminosity planed for the SLHC the experiments will require high data rate links and electronic components capable of sustaining high radiation doses. The GBT ASICs addresses this issue implementing a radiation-hard bi-directional 4.8 Gb/s optical fibre link between the counting room and the experiments. The paper describes in detail the GBT architecture and will present an overview of the various components that constitute the GBT chipset.
        Speaker: Mr Paulo Moreira (CERN)
        Paper
        Slides
      • 83
        The Versatile Transceiver Proof of Concept
        SLHC experiment upgrades will make substantial use of optical readout to enable high-speed data readout and control. The Versatile Link project will develop and assess optical link architectures and components suitable for deployment at SLHC. The on-detector element will be bidirectional opto-electronic module: the Versatile Transceiver that will be based on a commercially available module type minimally customized to meet the constraints of the SLHC on-detector environment in terms of mass, volume, power consumption, operational temperature and radiation environment. We report on the first proof of concept phase of the development, showing the steps towards customization and first results of the radiation resistance of candidate optoelectronic components.
        Speaker: Dr Jan Troska (CERN)
        Paper
        Slides
      • 84
        Passive Optical Networks in Particle Physics Experiments
        In this paper we propose a generic Passive Optical Network (PON) platform for the distribution of synchronous, fast rate signals within particle physics experiments. Our aim is to demonstrate a versatile network architecture that will be able to serve one or more applications in future high energy physics (HEP) experiments. In order for the current PON systems to be adapted to future HEP optical link requirements, a number of challenges regarding the physical layer and medium access layer implementations have to be overcome. A prototype PON is in the process of being built and its properties in accordance to HEP tentative requirements will be measured and reported.
        Speaker: Dr Ioannis Papakonstantinou (CERN)
        Paper
        Slides
    • OPTO WG
      • 86
        Future operating mode of the group
    • 13:05
      Lunch
    • TOPICAL
      • 87
        Low Power SoC Design
        The design of Systems-on-Chip (SoC) in very deep submicron technologies becomes a very complex task that has to bridge very high level system description to low level consideration due to technology defaults and variations. This talk will describe some of these low level main issues, such as dynamic and static power consumption, temperature, technology variations, interconnect, DFM, reliability and yield, and their impact on high-level design, such as the design of multi-Vdd, fault-tolerant, redundant or adaptive chip architectures. Low power SoC designed by CSEM will be presented for applications in three domains: wireless sensor networks, vision sensors and mobile TV.
        Speaker: Christian Piguet (Centre suisse d'Electronique et de Microtechnique SA)
        Paper
        Slides
      • 88
        Two-Phase Cooling of Targets and Electronics for Particle Physics Experiments
        An overview of the author’s decade of experience with two-phase cooling research for computer chips and power electronics will be described with its possible beneficial application to high energy physics experiments. Flow boiling in multi-microchannel cooling elements in silicon (or aluminium) have the potential to provide high cooling rates (up to as high as 350 W/cm2), stable and uniform temperatures of targets and electronics, and light-weight construction while also minimizing the fluid inventory. An overview of two-phase flow and boiling research in single microchannels and multi-microchannel test elements will be presented together with videos of these flows. The objective is to stimulate discussion on the use of two-phase cooling in these demanding applications, including the use of CO2.
        Speaker: Prof. John Richard Thome (Laboratory of Heat and Mass Transfer)
        Paper
        Slides
    • 15:45
      Break
    • POSTERS SESSION
      • 89
        A 10-bit 40MS/s pipelined ADC in a 0.13µm CMOS process
        This paper presents a 10-bit analogue to digital converter (ADC) that will be integrated in a general purpose charge readout ASIC that is the new generation of mixed-mode integrated circuits for Time Projection Chamber (TPC) readout. It is based on a pipelined structure with double sampling and was implemented with switched capacitor circuits in eight 1.5-bit stages followed by a 2-bit stage. The power consumption is adjustable with the conversion rate and varies between 15 and 34mW for a 15 to 40MS/s conversion speed. The ADC occupies a silicon area of 0.7mm2 in a 0.13µm CMOS process and operates from a single 1.5V supply.
        Speaker: Mr Hugo Franca Santos (CERN)
        Paper
        Poster
      • 90
        A 12 µm pitch CMOS Pixel Sensor Designed in the 3DIT for the ILC Vertex Detector
        CMOS Monolithic Active Pixel Sensors (MAPS) combined with 3D Integrated Technologies (3DIT) offer new opportunities to meet the challenging requirements of the next generation pixel technologies. This paper presents a 3D CMOS pixel sensor design adapted to the innermost layer of the ILC vertex detector. It contains a matrix of 96x256 pixels; each integrating, in a 12µm pitch, a sensing element, a preamplifier, a shaper, a discriminator, a 5-bit Time-to-Digital-Converter (TDC) and a delayed readout microcircuit. It was realised in a commercial CMOS-130nm technology. The paper describes its architecture and expected advantages with respect to the 2D CMOS MAPS.
        Speaker: Mr Yunan FU (DRS-IPHC, University of Strasbourg, CRNS-IN2P3)
        Poster
      • 91
        A 40 MHz trigger-free readout architecture for the LHCb experiment
        LHCb is considering an upgrade towards a full 40 MHz readout. In this paper we investigate possibilities for a new Timing and Fast Control (TFC) system based on completely new technologies, and the consequences for the readout electronics. We define the requirements and propose an architecture allowing partitioning, complete readout control and event management. The backbone is based on bidirectional high-speed optical links using the latest FPGA transceivers. For the Front-End Electronics we advocate exploiting the bidirectional capability of the CERN GigaBit Transceiver to make the Readout Boards the TFC and the Control System interface to the Front-End.
        Speaker: Federico Alessio (CERN)
        Paper
      • 92
        A Digitally Calibrated 12 bits 35 MS/s Pipelined ADC with a 32 input multiplexer for CALICE Integrated Readout
        The necessity of full integrated electronics readout for the next ILC ECAL presents many challenges for low power mixed signal design. The analog to digital converter is a critical stage for the system going from the very front-end stages to digital memories. We present here a high speed converter configuration designed to multiplex 32 analog channels through one analog to digital converter. A CMOS 0.35µm process is used. The dynamic range is 2V over a 3.3V power supply, and the total power dissipation at 30 MHz is approximately 50mW. An analog power management is included to allow a fast switching into a standby mode that reduces the DC power dissipation by a ratio of three orders of magnitude (1/1000).
        Speaker: Mr Fatah Rarbi (IN2P3 / LPSC Grenoble)
        Paper
      • 93
        A facility and a web application for real-time monitoring of the TTC backbone status
        The Timing Trigger and Control (TTC) system distributes timing signals from the LHC Radio Frequency (RF) source to the four experiments. A copy of these signals is also transmitted to a monitoring system, installed in the Control Center in Prevessin, which provides continuous measurement of parameters such as Bunch Clock jitter and frequency, Orbit period in BC counts, transmission delay over fiber versus temperature. A web application has been designed to ensure real time remote monitoring and post-mortem analysis of these data. The paper discusses the architecture of the monitoring system including measurement setup as well as different concerns of data acquisition, storage and visualization.
        Speaker: Mr Piotr Jurga (CERN)
        Paper
        Poster
      • 94
        A low-cost multi-channel analogue signal generator
        A scalable multi-channel analogue signal generator is presented. It uses a commercial low-cost graphics card with multiple outputs in a standard PC as signal source. Each color signal serves as independent channel to generate an analogue signal. A custom-built external PCB was developed to adjust the graphics card output voltage levels for a specific task, which needed differential signals. The system furthermore comprises a software package to program the signal shape. The signal generator was successfully used as independent test bed for the ATLAS Level-1 Trigger Pre-Processor, providing up to 16 analogue signals.
        Speaker: Mr Felix Müller (Kirchhoff Institute for Physics, University of Heidelberg)
        Paper
        Poster
      • 95
        A new paradigm using GPUs for fast triggering and pattern matching at the CERN experiment NA62
        We describe a pilot project for the use of GPUs in an online triggering application at the CERN NA62 experiment, and the results of the first field tests together with a prototype data acquisition system.
        Speaker: Gianmaria Collazuol (INFN Sezione di Pisa (INFN))
      • 96
        A programmable 10 Gigabit injector for the LHCb DAQ and its upgrade
        The LHCb High Level Trigger and Data Acquisition system selects about 2 kHz of events out of the 1 MHz of events, which have been selected previously by the first-level hardware trigger. The selected events are consolidated into files and then sent to permanent storage for subsequent analysis on the Grid. The goal of the upgrade of the LHCb readout is to lift the limitation to 1 MHz. This means speeding up the DAQ to 40 MHz. Such a DAQ system will certainly employ 10 Gigabit or technologies and might also need new networking protocols: a customized TCP or proprietary solutions. A test module is being presented, which integrates in the existing LHCb infrastructure. It is a 10-Gigabit traffic generator, flexible enough to generate LHCb's raw data packets using dummy data or simulated data. These data are seen as real data coming from sub-detectors by the DAQ. The implementation is based on an FPGA using 10 Gigabit Ethernet interface. This module is integrated in the experiment control system. The architecture, implementation, and performance results of the solution will be presented.
        Speaker: Mr Vincent Pierre Delord (ISIMA-Clermont Ferrand)
        Paper
      • 97
        A Prototype Front-End Readout Chip for Silicon Microstrip Detectors Using an Advanced SiGe Technology
        The upgrade of the ATLAS detector for the high luminosity upgrade of the LHC will require a rebuild of the Inner Detector as well as replacement of the readout electronics of the Liquid Argon Calorimeter and other detector components. We proposed some time ago to study silicon germanium (SiGe) BiCMOS technologies as a possible choice for the required silicon microstrip and calorimeter front-end chips given that they showed promise to provide necessary low noise at low power. Evaluation of the radiation hardness of these technologies has been under study. To validate the expected performance of these technologies, we designed and fabricated an 8-channel front-end readout chip for a silicon microstrip detector using the IBM 8WL technology, a likely choice for the ATLAS upgrade. Preliminary electrical characteristics of this chip will be presented.
        Speaker: Dr Alexander A. Grillo (Santa Cruz Institute for Particle Physics, University of California, Santa Cruz)
        Paper
        Poster
      • 98
        A self triggered amplifier/digitizer chip for CBM
        The development of front-end electronics for the planned CBM experiment at FAIR/GSI is in full progress. For the charge readout of the various subdetectors a new self triggered amplification and digitalization chip is being designed and tested. The chip will have 32-64 channels each containing a low power/low noise preamplifier/shaper front-end, an 8-9 Bit ADC and a digital post-processing based on a simple FIR-filter. The ADC uses a pipeline architecture based on novel current-mode storage cells. An overview of the architecture and the targeted applications is given and the status of the project is presented.
        Speaker: Mr Tim Armbruster (Heidelberg University)
        Paper
        Poster
      • 99
        A Zero Suppression Micro-Circuit for Binary Readout CMOS Pixel Sensors
        The EUDET-JRA1 beam telescope and the STAR vertex detector upgrade will be equipped with CMOS pixel sensors allowing to provide high density tracking adapted to intense particle beams. The EUDET sensor Mimosa26, is designed and fabricated in a CMOS-0.35µm Opto process. Its architecture is based on a matrix of 1152x576 pixels, 1152 column-level analogue-to-digital conversion by discriminators and a zero suppression circuitry. This paper concentrates on the data sparsification architecture, allowing a data compression factor ranging from 10 to 1000, depending on the hit density per frame. It can be extended to the final sensor for the STAR upgrade.
        Speaker: Mr Abdelkader HIMMI (DRS-IPHC, University of Strasbourg, CNRS-IN2P3)
        Paper
        Poster
      • 100
        AFTER, the Front-End ASIC of the T2K Time Projection Chambers
        The T2K (Tokai-to-Kamioka) experiment is a long baseline neutrino oscillation experiment in Japan, for which a near detector complex (ND280), used to characterize the beam, will be built 280m from the target in the off-axis direction of the neutrino beam produced using the 50 GeV proton synchrotron of J-PARC (Japan Proton Accelerator Research Complex). The central part of the ND280 is a detector including 3 large Time Projection Chambers based on Micromegas gas amplification technology with anodes pixelated into about 125,000 pads and requiring therefore compact and low power readout electronics. A 72-channel front-end Application Specific Integrated Circuit has been developed to read these TPCs. Each channel includes a low noise charge preamplifier, a pole zero compensation stage, a second order Sallen-Key low pass filter and a 511-cell Switched Capacitor Array. This electronics offers a large flexibility in sampling frequency (50 MHz max.), shaping time (16 values from 100 ns to 2 µs), gain (4 ranges from 120 fC to 600 fC), while taking advantage of the low physics events rate of 0.3 Hz. 6000 AFTER ASICs, have been manufactured in 2008 using a low-cost 0.35 μm CMOS technology,. They are currently being integrated on the TPCs for a start of commissioning at the end of the year 2009 in Japan.
        Speaker: Mr Eric Delagnes (CEA/Irfu)
        Paper
      • 101
        ALICE TPC CONTROL AND READOUT SYSTEM
        ALICE is a dedicated heavy-ion experiment at CERN LHC. It aims to reproduce the state of matter shortly after the Big Bang, i.e. the quark-gluon plasma. Each lead-lead collision will produce the order of ten thousand new particles. Detailed study of the event requires precise measurements of the particle tracks. An 95m3 Time Projection Chamber (TPC) with more than 500 000 read-out pads was built as the main central barrel tracker. Collisions can be recorded at a rate of up to about 1 kHz. The front-end electronics, designed from FPGAs and custom ASICs, performs shaping, amplification, digitalization and digital filtering of the signals. The data is forwarded to DAQ via 216 1.25 Gb/s fiber-optical links. Configuration, control and monitoring is done by an embedded Linux system. The close proximity of the electronics to the collisions exposes it to radiation, which required radiation tolerant design strategies. First results on the performance of the front-end electronics and the distributed detector control system are presented.
        Speaker: Dag Toppe Larsen (University of Bergen)
        Paper
        Poster
      • 102
        An FPGA-based Emulation of the G-Link Chip-Set for the ATLAS Level-1 Barrel Muon Trigger
        The ATLAS Level-1 barrel muon trigger is built as a synchronous pipeline and includes some high-speed serial links in order to transfer data from the detector to the counting room. The links are based on the GLink chip-set, which transfers data with a fixed and deterministic latency. Despite its unique timing features, the production discontinued and no compatible off-the-shelf chip-sets are available. The transmission side of the links is buried on-detector and will not be upgraded, however a replacement for the receivers in the counting room in case of failures is needed. We developed a replacement solution for GLink transmitters and receivers, based on the gigabit serial transceivers (GTP) embedded in a Xilinx Virtex5-LXT Field Programmable Gate Array (FPGA). In the LHC experiments, and in general wherever an experiment-wide clock is distributed, our link is able to transmit data with a fixed latency, even after a loss of lock or a power cycle. We present our architecture, showing the GTP internal configuration and the logic in the FPGA fabric needed for the protocol emulation. We compare the GLink and the GTP transmitter eye-diagrams and we discuss the results of Bit Error Rate (BER) and jitter measurements on hybrid (Glink vs. GTP) and homogeneous (GTP vs. GTP) links.
        Speaker: Dr Raffaele Giordano (Universita' di Napoli Federico II and INFN, Napoli)
        Paper
      • 103
        An integrated DC-DC step-up charge pump and step-down converter in 130 nm technology
        After the LHC luminosity upgrade the number of readout channels in the ATLAS Semiconductor Tracker will be increased. Therefore a new solution for powering the readout electronics has to be found. The two main approaches for power distribution are under development, the serial powering of a chain of modules and the parallel powering with DC-DC conversion. In both cases switched-capacitor converters are used. We present the design study of step-up charge pump and step-down converter optimized due to power efficiency, which is as high as 84% for step-up and 92% for step-down converter. Finally a model describing powering solutions mentioned above is going to be developed.
        Speaker: Mr Michal Bochenek (CERN)
        Paper
        Poster
      • 104
        ASPIC: LSST camera readout chip Comparison between DSI and C&S
        The ASPIC chip has been designed to readout the 3.2Gpixels of the LSST camera focal plane. The dynamic range is more than 16 bit and the noise has to be less than 7µV rms with a crosstalk better than 0.05%. The architecture is based on a double correlated sampling. 2 methods have been investigated: differential output Dual Slope Integrator which has been chosen to be the LSST baseline and Clamp and Sample. We plan to perform a deep comparison between these methods and therefore 2 ASICs have been designed in 5V compliant CMOS 0.35µm.
        Speaker: Mr François WICEK (LAL IN2P3 CNRS)
      • 105
        ATLAS Silicon Microstrip Tracker Operation
        The ATLAS experiment at the CERN Large Hadron Collider (LHC) has started taking data last autumn with the inauguration of the LHC. The SemiConductor Tracker (SCT) is the key precision tracking device in ATLAS, made up from silicon micro-strip detectors. The completed SCT has been installed inside ATLAS. Since then the detector was operated for many months under realistic conditions. Calibration data has been taken and analysed to determine the noise performance of the system. In addition, extensive commissioning with cosmic ray events has been performed both with and without magnetic field. The current status of the SCT will be reviewed, including results from the latest data-taking, and from the detector alignment. The SCT commissioning and running experience will then be used to extract valuable lessons for future silicon detector projects.
        Speaker: Dr Peter Vankov (University of Liverpool)
        Paper
        Poster
      • 106
        Buffer Control Chip (BCC) for the ATLAS Tracker Upgrade
        The ATLAS Tracker Upgrade project is developing large modules of up to two hybrids each. Each hybrid comprises two columns of ABCN-25 readout ASICs, each with a data rate twice the bunch-clock. A hybrid readout link thus handles two streams at quadruple the bunch-clock rate. To allow hybrids to operate at different potentials (as required by serial-powering), control signals make use of a novel AC coupled DC LVDS scheme. The BCC ASIC, designed to provide signal buffering, clock multiplication and data multiplexing, is described. Functionality, operation and results of testing and integration onto a tracker module will be presented.
        Speaker: Mr Matt Warren (UCL)
      • 107
        Characterization of Semiconductor Lasers for Radiation Hard High Speed Transceivers
        In the context of the versatile link project, a set of semiconductor lasers were studied and modeled aiming at the optimization of the laser driver circuit. High frequency measurements of the laser diode devices in terms of reflected and transmission characteristics were made and used to support the development of a model that can be applied to study their input impedance characteristics and light modulation properties. Furthermore the interaction between the laser driver, interconnect network and the laser device itself can be studied using this model. Simulation results will be compared to measured data to validate the model and methodology.
        Speaker: Mr Sergio Silva (CERN)
        Paper
        Poster
      • 108
        Charge Pump Clock Generation PLL for the Data Output Blocks of the Upgraded ATLAS Front-End in 130nm CMOS
        FE‐I4 is the 130nm ATLAS pixel IC currently under development for upgraded LHC luminosities. FE‐I4 is based on a low‐power analog pixel array and digital architecture concepts tuned for higher hit rates. An integrated PLL has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40MHz bunch crossing reference. This block is designed for low‐power, low‐area and handles high radiation levels. After a general FE‐I4 introduction, the presentation will focus on FE‐I4 output blocks and a first prototype submitted early 2009.
        Speaker: Andre Konrad Kruth (Physikalisches Institut der Universität Bonn, Nussallee 12, D - 53115 Bonn, Germany)
        Paper
      • 109
        CMD-3 First Level Trigger Infrastructure
        The cryogenic magnetic detector CMD-3 developed for experiments on elektron-pozitronnom collider VEPP-2000 is under construction at Budker Institute of Nuclear Physics now. This paper describes the modules which are forming an infrastructure and datapath of the First Level Trigger (FLT) of CMD-3. There are few types of modules specially developed for detector subsystems. These modules are intended for data gathering and processing of arguments of FLT, support of testing and precision calibration of FLT efficiency. The special attention is devoted to transmission synchronization of data pipelining, FLT reliability and efficiency on-line checks.
        Speaker: Mr Alexey Kozyrev (BINP)
      • 110
        Commissioning of the CSC Level 1 Trigger Optical Links at CMS
        The Endcap Muon (EMU) Cathode Strip Chamber (CSC) sub-detector at the CMS experiment at CERN has been fully installed and operational since summer of 2008. The system of 180 optical links connects the middle and upper levels of the CSC Level 1 Trigger chain. Design and commissioning of all optical links presents several challenges, including reliable clock distribution, link synchronization and alignment, status monitoring and system testing. We gained a lot of experience conducting various tests, participating in local and global cosmic runs and initial stage of the LHC operation. In this paper we present our hardware, firmware and software solutions and first results of the optical link commissioning.
        Speaker: Mikhail Matveev (Rice University)
        Paper
      • 111
        DC-DC switching converter based power distribution vs Serial power distribution: EMC strategies for SLHC tracker up-grade
        This paper presents a detailed and comparative analysis from the electromagnetic compatibility point of view of the proposed power distributions for the SLHC tracker up-grade. The main idea is to identify and quantify the noise sources, noise distribution at the system level and the sensitive areas in the front-end electronics corresponding to both proposed topologies: The DC-DC converter based power distribution and the serial power distribution. These studies will be used to define critical points on both systems to be studied and prototyped to ensure the correct integration of the system taking critically into account the electromagnetic compatibility. This analysis at the system level is crucial to ensure the final performance of the detector using non conventional power distributions and to avoid interference problems and excessive losses that can lead to failures or expensive unpractical solutions.
        Speaker: Dr Fernando Arteche (Instituto Tecnológico de Aragón)
        Paper
      • 112
        DEPFET Mini-matrix Readout System
        The Mini-matrix readout system is being developing for measuring characteristics of a small (3.5 x 3.5 mm) prototype of a DEPleted Field Effect Transistor (DEPFET) sensor for particle detection. The small sensor will have 8 x 6 active pixels allowing studies of the DEPFET structure behaving and processes during sensor operation. The Mini-matrix readout setup should allow us to make a precision collected charge measurement in each pixel with low noise, charge shearing among multiple pixels, clustering, charge-loss measurement, find optimal voltage values and timing of driving signals and should allow us to make a computer post-analysis as a correlated sampling, averaging, etc. The system is made of a commercial and custom-made blocks as a PC with an 8-channel 14-bit 125 Msps PCI data acquisition card, FPGA control card, current readout and switching circuit and differential to single-ended converter. The custom-made current readout circuit is made of 8 low noise trans-impedance readout amplifiers and the switching circuit contains 12 individual analog switches that are necessary to control the Gate and Clear electrodes of the DEPFET Mini-matrix sensor. The measuring system will be controlled and configured by PC. Total input noise should be below 20 e- (electrons). All 8 channels will be digitalized by 14-bit ADCs with 125 Msps for each channel in parallel with frame readout time 20 s. The switching circuit will have possibility of gate voltages timing with resolution of 10 ns and allows gate signals overlapping. Subtracting voltage for the pedestal current subtraction will be digitally reconfigurable. The system concept is simple, based on the previous single pixel measuring setups and should provide fast realization and precise results.
        Speaker: Mr Jan Scheirich (Charles University in Prague, Faculty of Mathematics and Physics)
      • 113
        Design and measurements of 10 bit pipeline ADC for the Luminosity Detector at ILC
        The design and preliminary measurement results of a prototype 10 bit pipline ADC for the Luminosity Detector (LumiCal) at the International Linear Collider (ILC) are presented. The motivation for the chosen architecture is presented and followed by the description of the core blocks. The prototype was fabricated in 0.35 um CMOS technology. The preliminary measurements of static (INL, DNL) and dynamic (SHNR, THD) parameters were performed to understand and quantify the circuit performance. The ADC was found to be fully functional for sampling frequencies up to about 40 MHz. The measurements performed at 30 MHz sampling showed the INL below 1 LSB and the DNL below 0.5 LSB.
        Speaker: Mr Szymon Kulis (Fac. of Phys. & Applied Comp. Sci.-AGH Univ. of Science & Techno)
        Paper
        Poster
      • 114
        Design of the CMS-CASTOR sub detector readout system by reusing existing designs
        The CMS CASTOR detector is a small calorimeter located at 14.3 meters from the interaction point behind the HF detector. The CASTOR project was only approved mid of 2007. Cherenkov radiation in a sampling structure is used to measure the energy as the HF does. Logically one would use the same readout hardware as used for HF. But also other architectures were considered. Given the limited resources and time, developments from scratch were excluded. This talk presents an overview of the implementation of the readout chain as well as the considerations for the different choices. The HF front end system was finally chosen. It sends all the digitized samples via optical links to the counting room for further processing. The HF architecture of the data selection and processing didn't fit so well our requirements due to different segmentation and costs. A development by the TOTEM collaboration and by the CMS pre-shower was more close to our needs in respect to flexibility, availability and material cost. This architecture needed only a small hardware adaptation as well an adaptation of the requirements. The full CASTOR detector will be installed in June 2009 and we expect that in September we can present the results of the commissioning of the detector.
        Speaker: Mr Wim Beaumont (Universiteit Antwerpen)
        Paper
        Poster
      • 115
        Detector Control System for the Electromagnetic calorimeter in CMS Experiment
        The challenging constraints on the design of the Electromagnetic Calorimeter (ECAL) of the Compact Muon Solenoid (CMS) experiment, such as rigorous temperature and voltage stability, imposed the development of a complex Detector Control System (DCS). In this paper the final layout and functionality of the CMS ECAL DCS are presented and the operational experience during the detector's commissioning and cosmic runs is discussed.
        Speaker: Georgi Leshev (Labor fur Hochenergiephysik)
        Paper
      • 116
        Development and commissioning of the ALICE pixel detector control system
        The Silicon Pixel Detector (SPD) is the section of the ALICE Inner Tracking System closest to the interaction point. In order to operate the detector in a safe way, a control system was developed in the framework of PVSS which allows monitoring a large number of parameters such as temperatures, currents, etc. The control system of the SPD implements interlock features to protect the detector against overheating and prevents operating it in case of malfunctions. The nearly 50000 parameters required to fully configure the detector are stored in a database which implements an automatic version of the configuration file after a new calibration run has been carried out. Several user interface panels were developed to allow also non-expert shifters to operate the detector easily and safely. This contribution provides a detailed description of the features and commissioning of the SPD control system.
        Speaker: Mr Claudio Bortolin (Universita degli Studi di Udine)
        Paper
      • 117
        Development of a 16:1 serializer for data transmission at 5 Gbps
        Radiation tolerant, high speed and low power serializer ASIC is used for optical digital data links systems in particle physics. Based on a commercial 0.25 μm silicon-on-sapphire CMOS technology, we designed a 16:1 serializer with a 5 Gbps serial data rate. We present the design details and post layout simulation results. This ASIC will be submitted for fabrication in August 2009. A shared PLL multi-channel serializer with a redundant scheme and ultra low power consumption is also discussed for applications with fibre ribbons to achieve a data throughput in tens of gigabit per second range.
        Speaker: Mr Datao Gong (Southern Methodist Univeristy)
        Paper
        Poster
      • 118
        Development of a high resolution transient recorder
        The GANDALF transient recorder with a resolution of 12bit@1Gsps has been developed to sample analog signal pulses with fast rising edges (3ns) and large dynamic ranges at the COMPASS experiment. Signals are digitized and processed by fast algorithms to extract pulse arrival times and amplitudes in real-time and to generate experiment trigger signals. With 8 analog channels, deep memories and a high data rate interface, this 6U-VME/VXS module is not only a dead time free readout system but also has huge numerical capabilities provided by the implementation of a Virtex5-SXT FPGA to disentangle possible pile-up pulses and determine timing information with a time resolution in the picosecond range.
        Speaker: Mr Sebastian Schopferer (University of Freiburg)
        Paper
        Poster
      • 120
        Electronic development for the upgrade of the LHCb Vertex detector.
        The LHCb experiment plans to upgrade the entire detector and increase its running luminosity by a factor 10, by 2015/2016. This will require a full scale replacement of the front end electronics, to enable all detector information to be read out at 40 MHz and combined in the first level trigger executed on a PC-farm. In addition, the parts of the detector which suffer from radiation damage or excessive occupancy at high luminosity will be upgraded appropriately. One very important component of the upgrade is the replacement of the silicon vertex detector, possibly to a pixelated device. R&D is underway to exploit the Timepix pixel detector recently developed by the Medipix2 collaboration. This chip, in combination with a pixelated silicon detector is very suitable for such a high energy physics application. The small pixel size of 55 x 55 micron together with the time over threshold charge measurement is expected to give very precise spatial resolution which is well matched to the requirements of LHCb. Some adaptions to the chip design are required to match the 40MHz readout rate and move from 250 nm technology to smaller feature sizes. The deep submicron technology has good potential to survive the radiation environment of up to 400 MRad, and future developments in 130 or 90 nm technology will provide increased radiation resistance and reduced power, which will be advantageous for the detector design. The potential to hybridise the design with the use of through silicon vias further enhances the efficiency and material budget of the detector. This talk will report on the planned developments, and on a number of testbeams scheduled for summer 2009 to establish the proof of principle of the use of Timepix for the high energy physics environment. Further electronics developments for the LHCb upgrade, such as alternative electronics chips, the planned use of FPGAs and the further extension of the Timepix for possible use in the RICH photon detector readouts will also be touched on.
        Speaker: Mr Jan Buytaert (CERN)
      • 121
        Error-free 10.7 Gb/s digital transmission over 2 km optical link using an ultra-low-voltage electro-optic modulator
        We demonstrate the feasibility of 10.7 Gb/s error-free (BER < 1e-12) optical transmission on distances up to 2 km using a recently developed ultra-low-voltage commercial electro-optic modulator (EOM) that is driven by 0.6 Vpp and with an optical input power of 1 mW. Thus, the modulator could be driven directly from the detectors’ board signals without the need of any further amplification reducing significantly the power dissipation and the material budget.
        Speaker: Prof. Marco Meschini (Istituto Nazionale di Fisica Nucleare, Firenze, Italy)
        Paper
        Poster
      • 122
        Hardware studies for the upgrade of the ATLAS Central Trigger Processor
        The ATLAS Central Trigger Processor (CTP) is the final stage of the first level trigger system which reduces the collision rate of 40 MHz to a level-1 event rate of 75 kHz. The CTP makes the Level-1 trigger decision based on multiplicity values of various transverse-momentum thresholds received from the calorimeter and muon trigger sub-systems using programmable selection criteria. In order to improve the rejection rate for the first phase of the planned luminosity upgrade of the LHC to 3 x 1034 cm-2 s-1, one of the options being studied consists of adding a topological trigger processor, using Region-Of-Interest information from the calorimeter and potentially also the muon trigger. This will also require an upgrade of the CTP in order to accommodate the additional trigger inputs. The current CTP system consists of a 9U VME64x crate with 12 custom designed modules where the functionality is largely implemented in FPGAs. The constraint for the upgrade study was to reuse the existing hardware as much as possible while not exceeding the latency envelope of 100 ns by a significant amount. This is achieved by operating the backplane at twice the design frequency and required developing new FPGA firmware for several of the CTP modules. We present the design and performance of the firmware for the input, monitoring and core modules of the CTP as well as results from initial tests of the upgraded system.
        Speaker: Mr Stefan Haas (CERN)
        Paper
        Poster
      • 123
        High-Speed Serial Optical Link Test Bench Using FPGA with Embedded Transceivers
        Serial optical data transmission provides a solution to High Energy Physics experiments' readout systems with high bandwidth, low power, low mass and small footprint. It will commonly be used in detector upgrades for the SLHC. In the meanwhile, commercial FPGAs with embedded multi-gigabit transceivers have become accessible. We develop a test bench with such a device at its core to verify link configurations, evaluate radiation tolerant components and automate test procedures. The prototype's applications in irradiation tests and characterization tests such as online data analysis, bit error rate (BER) sensitivity, jitter extraction and bathtub curve are discussed in detail.
        Speaker: Ms Annie Xiang (Southern Methodist University)
        Paper
        Poster
      • 124
        Interference coupling mechanisms in Silicon Strip Detector – FEE. -CMS tracker “wings”: A leaned lesson for SLHC-
        The identification of the coupling mechanisms between noise sources and sensitive areas of the front-end electronics (FEE) in the previous CMS tracker sub-system is critical to optimize the design of integrated circuits and hybrids for the proposed SLHC Silicon Strip Tracker systems. This paper presents a validated model of the noise sensitivity of the Silicon Strip Detector-FEE of the CMS tracker to quantify the impact of the noise coupling mechanisms in the system immunity against electromagnetic interferences. This model has been validated based on simulations using finite element models and immunity tests conducted on prototypes of the Silicon Tracker End-Caps (TEC) and Outer Barrel (TOB) systems. The results of these studies show important recommendations and criteria to be applied in the design of future hybrids and modules to increase the immunity against electromagnetic noise.
        Speaker: Fernando Arteche (Instituto Tecnologico Aragon - Saragoza - Spain)
        Paper
      • 125
        Low power discriminator for ATLAS pixel chip
        The design of the front-end (FE) pixel electronics requires high speed, low power, low noise and low threshold dispersion. In this work, we propose a new architecture for the discriminator circuit. It is based on the principle of dynamic biasing and developed for the FE chip of the ATLAS pixel upgrade. This paper presents two discriminator structures where the bias current depends on the presence of a signal at the input of the discriminator. Since the activity in the FE chip is very low, the power consumption is greatly reduced.
        Speaker: Mohsine Menouni (CPPM, Aix-Marseille Université, CNRS/IN2P3, Marseille, France)
        Paper
      • 126
        Measurement of the performances of a Low-Power Multi-Dynamics Front-End for Neutrino Underwater Telescope Optical Modules
        A proposal for a system to capture signals in the Optical Module of an underwater neutrino telescope is described, with focus on power consumption and dynamics considerations. All considerations regarding the signals and their acquisition are made starting from the most general hypothesis possible, so that they will be valid for any underwater Cherenkov neutrino telescope. A front-end board, the FE-ADC, using a commercial ADC, has been designed and realized. It is aimed at the demonstration of the advantages of the proposed architecture fitting the specifications of power dissipation, multi input dynamics and signal reconstruction has been realized. The performances of this board have been accurately measured, both stand alone and coupled to the PMT foreseen by the NEMO collaboration, and are presented and discussed. The results meet the requirements and establish the basis for the definitive design of the final front-end architecture employing the SAS (Smart Analogue Sampler) chip.
        Speaker: Dr Valeria Sipala (I.N.F.N. Catania)
        Paper
      • 127
        Novel charge sensitive amplifier design methodology suitable for large detector capacitance applications
        Alternative current mode charge sensitive amplifier (CSA) topology and related methodology for use as pre-amplification block in radiation detection read out front end IC systems is proposed. It is based on the use of a current conveyor architecture providing advantageous noise performance characteristics in comparison to the typically used CSA folded caccode structure. In the proposed architecture the CSA output noise is independent of the detector capacitance value, allowing the use of large area detectors without affecting the system noise performance. Theoretical analysis and simulation based results are confirmed by measurements on a prototype demonstrating the advantageous performance in relation to the traditional voltage mode structures mainly in terms of the noise performance dependency on the detector capacitance value.
        Speaker: Dr Thomas NOULIS (Electronics Lab. , Physics Dept., Aristotle Univ. of Thessaloniki, 54124 Thessaloniki Greece)
        Paper
      • 128
        OMEGAPIX : 3D electronics chip for pixel readout
        The OMEGAPIX circuit is the first front end prototype ASIC designed at LAL (Orsay) using 3D technology for the ATLAS upgrade SLHC pixel project. This work has been done inside a new international consortium for development of Vertical Integrated Technologies for Electronics and Silicon SEnsors (VITESSE), which has gathered, not only 3 IN2P3 (France) institutes, but also Fermilab (USA) and INFN (Italy) HEP laboratories . One goal of the consortium is to explore the range of design options available that could fit the physics requirement of future high energy colliders. LAL focused its efforts on the specific approach of sub-micron readout circuit dedicated for innovative high granular planar pixel sensors for Atlas upgrade pixel detector. This circuit has been submitted on May 2009. It is build in a two tier IC stacks: one analogue layer and one digital layer. For the manufacturing of the 2D part, it has been realized in 0.13um Chartered technology. For the 3D part the Tezzaron process has been used. The process is wafer to wafer technology, face to face, via first and uses Copper-Copper bonds. The circuit embeds 64x24 readout channels that have been developed to match the following requirements : low noise (100 e-), low threshold (1000 e-), very low power consumption (3 uW/ch) and a high granularity (50x50 um). This electronics chip will also allow us to study various flavours of transistors types (normal, low VT, 3p3) and their behaviour when exposed at high radiation levels compatible with SLHC doses. One other expected improvement of the 3D technology that will be checked is the reduction of substrate coupling between analogue and digital parts and thus should allow us to lower efficiently the pixel signal threshold. To reach these requirements, a simplified common source configuration has been designed to perform the charge preamplifier and the shaper. A special care has been taken for the minimization of the global capacitance, and, for the shaper, a variable gain and a DC level adjustment have been designed. Design considerations, simulation and hopefully first tests results will be presented. Authors : Lounis Abdenour, Christophe de La Taille, Gisèle Martin-Chassard, Yixian Guo, Damien Thienpont
        Speaker: Mr Damien Thienpont (IN2P3/LAL)
        Paper
        Poster
      • 129
        On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS)
        In a detector system, clock distribution to sensors must be controlled at a level allowing proper sensors synchronisation. In order to reach theses requirements for the HFT (Heavy Flavor Tracker) upgrade at STAR (Solenoidal Tracker at RHIC), it has been proposed to distribute a low frequency clock at 10 MHz which will be multiplied in each sensor by a PLL to 160 MHz. A PLL was designed for low period jitter less than 20 ps rms and low power consumption of 7mW. This paper presents the architecture and the measurement results of the PLL fabricated in a 0.35µm CMOS process.
        Speaker: Dr Isabelle Valin (DRS-IPHC, University of Strasbourg, CNRS-IN2P3)
        Paper
        Poster
      • 130
        Position Measurements with Micro-Channel Plates and Transmission Lines using Pico-second Timing and Waveform Analysis
        Micro-Channel Plates anodes are coupled to fast transmission lines in order to reduce the number of electronics readout channels, and provide two-dimensions position measurements using centroids and two-ends delay timing. Tests using a laser and waveformanalysis have shown that resolutions of a few hundreds of microns along thetransmission line can be reached. This technique is planned to be used in novel Micro-channel Plates devices integrating the transmission lines as anodes.
        Speaker: Dr Jean-Francois Genat (University of Chicago)
        Paper
        Poster
      • 131
        Presentation of the “ROC” chips readout
        The OMEGA group at LAL has designed 3 chips for ILC calorimeters: one analog (SPIROC) and one digital (HARDROC) for the hadronic one and also one for the electromagnetic one (SKIROC). The readout and the management of these different chips will be explained. To minimize the lines between the ASICs and the DAQ, the readout is made thanks to 2 lines which are common for all the chips: Data and TransmitOn. As the chips are daisy chained, each chip is talking to the DAQ one after the other. When one chip has finished its readout, it starts the readout of the chip just after. Moreover, during this readout, only the chip which is talking to the DAQ is powered: this is made thanks to the POD (Power On Digital) module in the ASIC. In the ILC mode, readout sequence is active during inter bunch crossing (like ADC conversion). Another chip designed for PMM2 R&D program (PARISROC) integrates a new selective readout: that’s mean only hit channels are sent to the DAQ in a complete autonomous mode.
        Speaker: Mr Stéphane Callier (Laboratoire de l'Accélérateur Linéaire)
        Paper
        Poster
      • 132
        Radiation hardness studies of a 130 nm Silicon Germanium BiCMOS technology with a dedicated ASIC
        We present in this paper radiation hardness studies on devices of the 130 nm 8WL Silicon Germanium (SiGe) BiCMOS technology from IBM. This technology has been proposed as one of the candidates for the Front-End (FE) readout chip of the upgraded Inner Detector (ID) and the Liquid Argon Calorimeter (LAr) of the ATLAS Upgrade experiment. Gamma, neutron and proton radiation experiments have been scheduled using a purposely designed ASIC in order to take into account all radiation damage mechanisms of the devices. A study of the influence of thermal neutrons on the radiation hardness of devices of this technology has also been scheduled.
        Speaker: Mr Sergio Díez (Instituto de Microelectrónica de Barcelona - Centro Nacional de Microelectronica IMB-CNM (CSIC), Spain)
        Paper
        Poster
      • 133
        Readout and Data Processing Electronics for the Super-Belle Silicon Vertex Detector
        A prototype readout system has been developed for the future Super- Belle Silicon Vertex Detector at the Super-KEK-B factory in Tsukuba, Japan. It will receive raw data from double-sided sensors with a total of approximately 250,000 strips read out by APV25 chips at a trigger rate of up to 30kHz and perform strip reordering, pedestal subtraction, a two-pass common mode correction and zero suppression in FPGA firmware. Moreover, the APV25 will be operated in multi-peak mode, where (typically) six samples along the shaped waveform are used for precise hit-time reconstruction which will also be implemented in FPGAs using look-up tables.
        Speaker: Dr Markus Friedl (HEPHY Vienna)
        Paper
        Poster
      • 134
        Silicon Photomultiplier integrated readout chip (SPIROC) for the ILC: characterization and mesurements
        The SPIROC chip is a dedicated very front-end electronics for an ILC technical prototype hadronic calorimeter with Silicon Photomultiplier (or MPPC) readout. This ASIC is due to equip a 2,000-channel demonstrator in 2009. The SPIROC chip is the successor of the ILC_SiPM ASIC presently used for the ILC AHCAL physics prototype incorporating additional features like autotriggering, pipelines, digitization as well as power pulsing. Realized in 0.35um SiGe technology it is designed in order to fulfill ILC final detector requirements of large dynamic range, low noise, low power consumption, high precision and large channel numbers. The SPIROC is a 36-channel chip. Each channel has bi-gain amplification, auto-triggering capability, a 16-bit depth analog memory array and a 12-bit Wilkinson ADC. It allows time and charge measurements at the same time with digitized data results. The digitization is controlled and read out by the digital part of the chip. After the submission in June 2007, extensive measurements have been carried out to characterize the chip. Results on linearity, noise, triggering, timing capability and the A/D interface etc. will be presented. The chip has been proven to be successful in calorimeter calibration as well as real physics experiments.
        Speaker: Mr Stépahne Callier (Laboratoire de l'Accélérateur Linéaire)
        Paper
      • 135
        Simple parallel stream to serial stream converter for Active Pixel Sensor readout.
        This paper describes a new electronics module for converting a parallel data flow to a serial stream in the USB 2.0 High Speed protocol. The system provides a connection between a PC USB port and a parallel interface of the DAQ board, which is used for investigation of performance of Active Pixel Sensors (APS) prototypes. The DAQ readout software supports Win XX OS and Linux OS. GUI examples have been prepared in the Lab Windows and Lab View environments. The module that was designed using virtual peripheral concept can be easily adapted for many similar tasks.
        Speaker: Vasilii Kushpil (Academy of Sciences of the Czech Republic (ASCR))
        Paper
        Poster
      • 136
        Standalone radiation monitors for electronics in High Energy Physics
        Based on the principle of the RADMON on line radiation monitoring system for the LHC, a new type of low cost, battery powered radiation monitors has been designed that do not need external cabling. In this paper we will outline the hardware design, summarise on the radiation tolerant components and tests and describe the associated usb interace and labview software. First operational data from the CERN accelerators will be given and compared to monte carlo simulations.
        Speaker: Dr Thijs Wijnands (CERN)
        Paper
        Poster
      • 137
        Study Radiation Hardness Performance of PiN diodes for the ATLAS Pixel Detector at SLHC
        We study the radiation hardness of PiN diodes which are part of the optical link. These components were irradiated by 200 MeV protons up to 8.2 x 10exp(15) 1-MeV neq/cm2 ( 84 MRad). The responsivity of PiN diodes are measured as a function of the radiation dose to estimate life time reliability of diodes.
        Speaker: Mr Babak Abi (Oklahoma State University)
        Paper
      • 138
        The ATLAS ReadOut System - improved performance with the switch-based architecture
        About 600 custom-built ReadOut Buffer INput (ROBIN) PCI boards are used in the Data-Collection of the ATLAS experiment at CERN. In the standard setup requests and event data are passed via the PCI interfaces. The performance meets the requirements, but may need to be enhanced for more demanding use cases. Modifications in the software and firmware of the ROBINs have made it possible to improve the performance by using the on-board Gigabit Ethernet interfaces for passing part of the requests and of the data. Details of these modifications as well as measurement results will be presented.
        Speaker: Mr Nicolai Schroer (Ruprecht Karls Universitaet Heidelberg)
        Paper
        Poster
      • 139
        The Control System for a new Pixel Detector at the sLHC
        For the sLHC upgrade a new ATLAS Pixel Detector is planned, which will require a completely new Control System. The requirements, a first concept and a layout will be presented. We will focus on a control chip which necessarily has to be implemented in the new Detector Control System. A setup of discrete components has been built up to investigate and verify the chip's requirements. First measurements with this setup will be presented.
        Speaker: Mrs Jennifer Boek (Bergische Universitaet Wuppertal)
        Paper
        Poster
      • 140
        The design of a low power, high speed phase locked loop
        Detector front-end readout upgrades for the ATLAS Liquid Argon Calorimeter call for radiation tolerant, high speed, and low power optical digital data links. In the development for a high speed, low power serializer ASIC, we have designed an LC-based phase locked loop (PLL) using a commercial 0.25-µm Silicon-on-Sapphire (SoS) CMOS technology. Post-layout simulation indicates that we can achieve a tuning range of 4.1 – 5.3 GHz with power consumption below 20 mW. The PLL will be submitted for fabrication in August, 2009. The design, optimization, and simulation results are presented.
        Speaker: Mr Tiankuan Liu (Southern Methodist University)
        Paper
        Poster
      • 141
        The Fast Tracker Architecture for the LHC baseline luminosity
        Hadron collider experiments search for extremely rare processes hidden in much larger background levels. Only a tiny fraction of the produced collisions can be stored on tape and an enormous real-time data reduction is needed. This requires massive computing power to minimize the online execution time of complex algorithms. A multi-level trigger is an effective solution for an otherwise impossible problem. The Fast Tracker (FTK) [1], [2] has been proposed for high quality track finding at very high rates (Level-1 output rates) for LHC experiments. FTK will use FPGA and ASIC devices in order to complement CPUs. FTK beats the combinatorial challenge with special associative memories, where parallelism is exploited to the maximum level. They compare the track detector hits to all pre-calculated track patterns at once. The system design is defined and proposed for high-luminosity studies including low-Pt B physics and high-Pt signatures for Level-2 selections: b-jets, tau-jets, and isolated stiff light leptons. We test FTK algorithms using Atlas full simulation with WH and Hqq events at 10^-34 cm^-2 s^-1. The reconstruction quality is evaluated comparing FTK results with the tracking capability of an offline tracking algorithm. We show that similar resolutions and efficiencies are reached by FTK. The online use of the whole silicon tracker is necessary to obtain the low fake rate typical of the offline. We study the event timing inside the pipelined, data-driven FTK architecture. We compare different architectures to optimize the latency and hardware system size. FOOT Notes. [1] The fast tracker processor for hadronic collider triggers, Annovi, A et al.; ; Nuclear Science, IEEE Transactions on Volume 48,  Issue 3,  Part 1,  June 2001 Page(s):575 - 580 [2] Hadron collider triggers with high-quality tracking at very high event rates, Annovi, A. et al.; Nuclear Science, IEEE Transactions on Volume 51,  Issue 3,  Part 1,  June 2004 Page(s):391 - 400 [3] Performance of the Proposed Fast Track Processor for Rare Decays at the ATLAS Experiment, Brubaker, E.; Nuclear Science, IEEE Transactions on Volume 55,  Issue 1,  Part 1,  Feb. 2008 Page(s):145 - 150
        Speaker: Mr Guido Volpi (INFN, Sezione di Pisa-Unknown-Unknown)
      • 142
        The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHC experiments
        This work describes the architecture of the GigaBit Transceiver – Slow Control Adapter (GBT–SCA) ASIC suitable for the control and monitoring applications of the embedded front-end electronics in the future SLHC experiments. The GBT–SCA is part the GBT chipset currently under development for the SLHC detector upgrades. It is designed for radiation tolerance and it will be fabricated in a commercial 130 nm CMOS technology. The paper discusses the GBT-SCA architecture, the data transfer protocol, the ASIC interfaces, and its integration with the GBT optical link.
        Speaker: Dr Alessandro Gabrielli (CERN EP-MIC - Physics Department & INFN Bologna)
        Paper
        Poster
      • 143
        The Online Error Control and Handling of the ALICE Pixel Detector
        The SPD forms the two innermost layers of the ALICE experiment. It is equipped with a total of 120 modules (half-staves) with a total number of 9.8 x 106 readout channels. Each half-stave is connected via three optical links to the off-detector electronics made of FPGA based VME readout cards (Routers). The Routers and their mezzanine cards provide the zero-suppression, data formatting and multiplexing and the link to the DAQ system. This paper presents the hardware and software tools developed to detect and process errors occurring at the level of the Router originating from either front-end electronics, DAQ or the off-detector electronics. The error handling system then automatically transmits this information to the detector control system and to dedicated MySQL database for further analysis.
        Speaker: Dr Michele Caselle (CERN - Università Degli Studi di Bari)
        Paper
      • 144
        The Prompt Trigger of the Silicon Pixel Detector for the ALICE Experiment
        The ALICE Silicon Pixel Detector (SPD) constitutes the two innermost layers of the ALICE experiment. It consists of 1200 pixel chips with a total of ~107 channels with a pixel size of 50x425 μm2. Each pixel chip transmits a Fast-Or signal upon registration of at least one pixel hit. These signals are extracted every 100 ns and processed by the Pixel Trigger (PIT) system. A signal is then sent within a latency of 800 ns to the Central Trigger Processor for the Level 0 trigger decision. This paper describes the commissioning of the PIT, the tuning procedure of the SPD modules to obtain a good efficiency of the Fast-Or signal, and results of operations in cosmic and beam runs.
        Speaker: Ms Costanza Cavicchioli (CERN)
        Paper
        Poster
      • 145
        Total dose effects on a deep-submicron SOI technology for Monolithic Pixel Sensor development
        A monolithic pixel detector in deep-submicron Silicon On Insulator (SOI) technology has been developed and characterized. This summary presents the first assessments of the effect of ionizing radiation as regards the total dose damage on single transistors in the technology used for the development of the first prototype chip. This work shows the decisive effect of the substrate bias condition during irradiation on the radiation induced damage on the electronics.
        Speaker: Mrs Serena Mattiazzo (Dipartim. di Fisica Galileo Galilei-Universita degli Studi di Pa)
        Paper
        Poster
      • 146
        Upgrade of the BOC for the ATLAS Pixel Insert-able B-Layer
        The first upgrade for the ATLAS pixel detector will be an additional layer, which is called IBL (Insert-able B-Layer). To readout this new layer having new electronics assembled an update of the readout electronics is necessary. The aim is to develop a system which is capable to read out at a higher bandwidth and also compatible with the existing system to be integrated into it. The talk will describe the necessary development to reach a new readout system, concentrating on the requirements of a newly designed Back of Crate card as the optical interface in the counting room.
        Speaker: Jens Dopke (University of Wuppertal)
        Paper
        Poster
      • 147
        Upgrade of the Cold Electronics of the ATLAS HEC Calorimeter for sLHC: Generic Studies on Radiation Hardness and Temperature Dependence.
        The signal amplification and summation electronics of the ATLAS Hadronic End-cap Calorimeter (HEC) is operated at the circumference of the HEC calorimeters inside the cryostats in liquid argon. The present electronics is designed to operate at irradiation levels expected for the LHC. For operation at the sLHC the irradiation levels are expected to be a factor 10 higher, therefore a new electronic system might be needed. The technological possibilities are investigated. From irradiation tests of the present HEC electronics it is known that it will operate up to a dose of 55 kGy of ionizing radiation and up to a neutron fluence of 3 * 10**14 n/cm**2, where it shows some degradation of performance. This matches well the requirements of up to 1.5 * 10**13 n/cm**2 for 10 years of LHC operation, including safety factors. For a subsequent sLHC running phase with 10 times higher expected irradiation levels, a more radiation hard HEC electronics will be needed. Therefore generic studies of different technologies have been carried out at the transistor level to understand the radiation hardness up to integrated neutron fluxes of ~2*10**16 n/cm**2 and the behaviour during operation at cryogenic temperatures. The S-parameter technique has been used to monitor the performance e.g. of gain and linearity during irradiation at room temperature. In addition, DC measurements before and after irradiation have been compared. Results of these tests and of accompanying noise tests are reported. In addition, results of S-parameter measurements will be reported operating the transistors in liquid nitrogen. Conclusions are drawn and the potential is assessed on the viability of using the tested technologies for carrying out the design of new HEC cold electronics for the sLHC.
        Speaker: Ms Agnes Rudert (Atlas HEC)
        Paper
        Poster
      • 148
        Wafer Screening of ABCN-25 readout ASIC
        The ABCN-25 chip was fabricated in 2008 in the IBM 0.25 micron CMOS process. One wafer was immediately diced to make chips available for evaluation with test PCBs and hybrids, programmes which are reported separately. Early indications based on the diced wafer suggested a percentage yield in the high nineties, however the community decided to screen the remaining wafers such that faulty die could be excluded from the module construction programme. This paper documents the test hardware and software, the procedures used to perform the screening and gives a brief overview of results.
        Speaker: Mr Peter Phillips (Particle Physics)
        Paper
      • 149
        A Radiation Tolerant 4.8 Gb/s Serializer for the Giga-Bit Transceiver
        This paper describes the data serializer of the GigaBit Transceiver (GBT) which has been under development for the LHC upgrade (SLHC). The circuit operates at 4.8 Gb/s and is implemented in a commercial 130 nm CMOS technology. The serializer occupies an area of 0.6 mm² and its power consumption is 300 mW. The paper focuses on the techniques used to achieve radiation tolerance and on the simulation method used to estimate the sensitivity to SETs.
        Speaker: Dr Ozgur Cobanoglu (CERN, PH-ESE-ME)
        Paper
        Poster
    • 19:00
      Conference event and Dinner
  • Friday, 25 September
    • Plenary Session 6 - Programmable Logic, Boards, Crates and Systems
      • 150
        Recent Advances in Architectures and Tools for Complex FPGA-based Systems (Invited Talk)
        Emerging FPGA architectures include large amounts of programmable logic and interconnect, dedicated memory, and digital signal processing slices, along with high-speed serial and parallel I/0, embedded microprocessors, integrated communication blocks, and advanced clocking capabilities. These emerging FPGA architectures and new FPGA development tools, which enable designs to be developed at a high level of abstraction, are enabling the design of very complex digital systems. In this talk, I will provide an overview of emerging FPGA architectures and describe some recently developed tools that facilitate the rapid design, integration, and testing of complex FPGA-based systems. I will also discuss how some of these FPGA architectures and tools are being utilized to facilitate the design and testing of advanced FPGA-based systems for particle physics.
        Speaker: Prof. Michael Schulte (College of Engineering - University of Wisconsin)
        Paper
        Slides
      • 151
        A flash high-precision Time-to-Digital Converter implemented in FPGA technology
        Time to Digital Converters (TDCs) are often required in many applications in High Energy and Nuclear Physics. Furthermore, they have been widely used in many scientific equipments such as Time-Of-Flight (TOF) spectrometers and distance measurements. Different configurations of tapped delay lines are widely used to measure sub-nanosecond time intervals both in ASIC and FPGA devices. However, the design process of an ASIC device can be expensive, especially if produced in small quantities, while FPGAs lower the development cost and offer high design flexibility. Rapid progress in FPGA electronics technology allowed achieving a time resolution values in between 50 ps and 500 ps . The architecture used in this paper beside being dead time is multi-hit and allows for a resolution of about 35 psec. We'll show in this paper its performance in terms of resolution, integral and differential non linearity
        Speaker: Dr Salvatore Loffredo (INFN)
        Paper
        Slides
      • 152
        Implementing the GBT data transmission protocol in FPGAs
        The GBT chip is a radiation tolerant ASIC that can be used to implement bidirectional multipurpose 4.8 Gb/s optical links for high-energy physics experiments. It will be proposed to the LHC experiments for combined transmission of physics data, trigger, timing, fast and slow control and monitoring. Although radiation hardness is required on detectors, it is not necessary for the electronics located in the counting rooms. Therefore, a study is being made to implement these GBT links on FPGAs. This paper will describe the GBT protocol implementation, the configuration of the transceivers on Altera Stratix II GX and Xilinx Virtex 4, the optimization of resource for multi-transceivers, the first data transmission tests and the source code availability.
        Speaker: Mr Frederic MARIN (CPPM)
        Paper
        Slides
      • 153
        FPGA-based Bit-Error-Ratio Tester for SEU-hardened Optical Links
        Reliable optical links for future High-Energy Physics experiments will require components qualified for use in radiation-hard environments. To cope with radiation induced single-event upsets, the physical layer protocol will include Forward Error Correction (FEC). Bit-Error-Ratio (BER) testing is a widely used method to characterize digital transmission systems. In order to measure the BER with and without the proposed FEC, simultaneously on several devices, a multi-channel BER tester has been developed. This paper describes the architecture of the tester, its implementation in Xilinx FPGA devices and discusses the experimental results.
        Speaker: Mr Csaba Soos (European Organization for Nuclear Research (CERN))
        Paper
        Slides
    • 11:00
      Late break
    • Plenary Session 7 - Reports from WGs
      • 154
        Report from Power WG
        Slides
      • 155
        Report from Opto WG
        Slides
      • 156
        Report from MUG
    • CLOSE OUT
      • 157
        CLOSE OUT
        Slides
    • 12:25
      Lunch
    • TUTORIAL - FPGA Tools and Techniques for High Performance Digital Systems (1)
      • 158
        FPGA Tools and Techniques for High Performance Digital Systems (Tutorial)
        This two-part tutorial will introduce the audience to FPGA tools and techniques that provide the ability to efficiently design, integrate, and test high performance digital systems. The first half of the tutorial will cover hardware design techniques and tools currently available from industry such as Xilinx ISE Foundation, PlanAhead Design Analysis, and ChipScope. The second half of the tutorial will cover advanced techniques and tools for complex digital system design, testing, and integration such as the Dataflow Interchange Format (DIF), the DSPCAD Integrative Command Line Environment (DICE), and Subversion (SVN) repositories. Tutorial participants will be introduced to tools and techniques for FPGA-based design, see examples of efficient HDL coding, testing, and integration practices, gain experience with using the tools, and. obtain an understanding of FPGA tool capabilities and challenges Although the focus of the tutorial will be on FPGA-based systems, many of the tools and techniques presented can also be used to design, test, and integrate ASICs, embedded software, and other types of digital system. No previous experience with FPGA design is required.
        Speakers: Anthony Gregerson (University of Wisconsin-Madison), Michael Schulte (College of Engineering - University of Wisconsin), Shuvra BHATTACHARYYA (University of Maryland)
    • 15:45
      Break
    • 16:15
      TUTORIAL - FPGA Tools and Techniques for High Performance Digital Systems (2)
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