21–25 Sept 2009
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France
Europe/Paris timezone
<strong>The deadline for paper submission has been extended to 23 October 2009</strong>

Session

Parallel Session A5 - ASICS

A5
24 Sept 2009, 09:45
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Presentation materials

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  1. Luigi Caponetto (INFN/CNRS)
    24/09/2009, 09:45
    ASIC's
    Oral
    A transient waveform sampler/recorder IC has been developed and realized in AMS C35 technology to be used in the front-end of a neutrino detector. It is based around a switched capacitors array unit sampling its voltage inputs at 200MHz external clock rate and transferring them at its outputs at 1/10th of the sampling rate. This unit is replicated inside the ASIC providing 4 independent...
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  2. Ms Selma Conforti Di Lorenzo (OMEGA/LAL/IN2P3/CNRS)
    24/09/2009, 10:10
    ASIC's
    Oral
    PARISROC is a complete read out chip, in AMS SiGe 0.35μm technology [1],for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by French national agency for research (ANR) and called PMm2:“Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles” [2]...
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  3. Mr Sebastien Crampon (LPC Clermont Ferrand)
    24/09/2009, 11:00
    ASIC's
    Oral
    This paper describes the Analog to Digital Converter developed for the front end electronic of the IN2P3 INNOTEP project by the “pole microelectronique Rhone-Auvergne”. (Collaboration LPC Clermont-Ferrand and IPNL Lyon). This ADC is a 4 stages, 2.5 bits per stage pipe line, with open loops track and holds and amplifiers. It runs at 100MSamples/s and has 8 bits of resolution. The stages...
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  4. Mrs Vanessa Tocut (CNRS/IN2P3/LAL-ORSAY)
    24/09/2009, 11:25
    ASIC's
    Oral
    The SNATS chip is designed to provide both a high resolution of 70ps RMS and a large dynamic range of 53 bits. The architecture is based on the association of 32 cell delay locked loops and of a 48-bit digital counter which are synchronized to a 160 MHz external clock. A 16 channel prototype has been designed in AMS 0.35 µm CMOS technology and its main performances are a Differential...
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  5. Mr Alessandro Gabrielli (CERN EP-MIC - Physics Department & INFN Bologna)
    24/09/2009, 11:50
    ASIC's
    Oral
    Here is described a novel approach to detect particles by means of a solid-state device susceptible to latchup-like effects. The stimulated ignition of latchup effects caused by external radiation has so far proven to be a hidden hazard. Here this is proposed as a powerful means of achieving the precise detection and positioning of a broad range of ionising particles. The cell can be...
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  6. Giovanni Mazza (INFN sezione di Torino, Italy)
    24/09/2009, 12:15
    ASIC's
    Oral
    A laser driver for data transmission at 5 Gb/s has been developed as a part of the GigaBit Transceiver (GBT) project. The GigaBit Laser Driver (GBLD) targets High Energy Physics (HEP) applications for which radiation tolerance is mandatory. The GBLD ASIC can drive both VCSELs and some types of edge emitting lasers. It is essentially composed of two drivers capable of sinking up to 12 mA each...
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  7. Mr Mohsine Menouni (CPPM, Aix-Marseille Université, CNRS/IN2P3, Marseille, France)
    24/09/2009, 12:40
    ASIC's
    Oral
    This paper presents a 4.8 Gbit/s optical receiver designed in a 0.13 µm CMOS process as part of the GBT project. The receiver consists of a transimpedance amplifier (TIA) and a limiting amplifier. A differential cascode structure with inductive peaking is adopted for the TIA to achieve high gain, high bandwidth and low input referred noise. Experimental results at room temperature show an open...
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