TWEPP-09 Topical Workshop on Electronics for Particle Physics

Session

Plenary Session 2 - Low Power Analog Design Techniques

P2

22 Sept 2009, 14:15

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

158. Low Power Analog Design in Scaled CMOS Technologies

Andrea Baschirotto (University of Milan-Bicocca)

22/09/2009, 14:15

ASIC's

Oral

The running CMOS technology scaling has a big impact in the design of analog circuits. Since scaled technologies offer big advantages to digital parts (reduce space, lower power consumption, etc...), complex mixed-signal systems are typically developed in the smallest minimum-gate-length technology. However these advantages for the digital part in a scaled technology correspond to a big...