Feb 20 – 22, 2017
FBK, Trento
Europe/Zurich timezone

Latest results from development of n^+-in-p planar pixel sensors and LGAD devices by KEK/HPK

Feb 20, 2017, 4:30 PM
30m
Aula Grande (FBK, Trento)

Aula Grande

FBK, Trento

Via Santa Croce, 77 38122 Trento ITALY

Speaker

Yoshinobu Unno (High Energy Accelerator Research Organization (JP))

Description

In this report, we present two topics: one is on the n^+-in-p planar pixels sensors with 50x50 or 25x100 um^2 pixels, and the other on the first trial of low-gain avalanche device (LGAD). The 50x50 or 25x100 um^2 pixels are laid out in a pattern of (50x50 or 25x100) + 50x450 um^2 pixels for the 2x (50x250) um^2 pixels of the FE-I4 ASIC. A number of patterns of biasing networks, including without, are implemented. The bias resistor with Polysilicon is made into a shape of vortex in an area of 50x50 um^2. These pixel sensors were flip-chipped and were gone through irradiation with protons of a fluence of 3x10^15 neq/cm^2 and test beams at CERN. The detection efficiency for the passing charged particles are evaluated and reported. LGAD devices (diodes and miniature strip sensors) were fabricated. The LGAD diodes were gone through the irradiation of gammas or neutrons. The responses were measured with LED lights. The first results are presented.

Work done by ATLAS-Japan Silicon Collaboration.

TRACK Planar Sensors

Primary author

Yoshinobu Unno (High Energy Accelerator Research Organization (JP))

Presentation materials