Advancements in CMOS fabrication over the past decade have led to a proliferation of new silicon detector concepts in recent years, leading beyond current hybrid pixel detectors with passive diode sensors. Each technology offers both advantages and drawbacks, and must be matched to the application in hand. One of those currently under consideration for the CLIC vertex detector is a commercial 180 nm High Voltage (HV-) CMOS process, where on-pixel circuitry is implemented in a deep n-well which shields it from the substrate. This scheme allows significant bias voltages to be applied to the device, facilitating fast charge collection and a depletion depth of up to several tens of microns. The readout scheme envisaged by CLIC is for capacitive coupling to a dedicated 65 nm CMOS readout ASIC, with the HV-CMOS acting as an “active” sensor. This presents challenges beyond the exploration of the CMOS technology: coupling between the chips must be controlled, necessitating further study on the device glueing and cross-capacitancies between neighbouring pixels. The chip planarity will directly affect the transmitted signal, in addition to the precision with which the devices are bonded. An overview of current R&D towards the reliable production of capacitive assemblies for CLIC will be presented, along with the next-generation ASICs which have recently been submitted for fabrication.