Oct 26 – 30, 2009
Lawrence Berkeley National Laboratory
America/Los_Angeles timezone

Intel HPC environment for Silicon Design and Key Learnings

Oct 28, 2009, 4:30 PM
Bldg. 66 Auditorium (Lawrence Berkeley National Laboratory)

Bldg. 66 Auditorium

Lawrence Berkeley National Laboratory

1, Cyclotron Road, Berkeley, CA, 94720 USA


Mr Shesha Krishnapura (Intel)


Silicon design technical complexity is increasing every year due to several new features and process technology shrinks. Additionally, the business drivers such as shorter product development time, reduced headcount, and lower cost is increasing pre-silicon verification, high degree of design automation, and global multi-site design teams. These two factors (technological and business) are astronomically increasing demand on computing and storage driving design computing to be engineered as an HPC environment. This presentation will cover Intel HPC design compute environment, generational improvements, and realized value in the areas of compute clusters, very high large memory servers, optimal network, and parallel storage.

Presentation materials