Choose timezone
Your profile timezone:
EP-ESE Electronics Seminars
Report on IEEE-ISSCC 2018: micro-nano-pico, we must go on
by
→
Europe/Zurich
13/2-005 (CERN)
Description
Several new trends have been presented at the main integrated-circuit design conference ISSCC in San Francisco. Data transmission makes big steps in speed and capacity, power conversion applies new materials that allow much larger steps. Downscaling of chips continues apparently still everywhere, but by using different approaches than in the 'easy' past. An SRAM in the so-called 7 nanometer node was reported, where 13.5nm EUV lithography was used instead of the multi-exposure 193nm ultraviolet light. A 1 Tb flash memory uses a thin stack of 96 layers. Imagers become smaller and more complex, and much cheaper as well. The particle physics community ought to study carefully what is going on, so that new possibilities can be exploited for future experiments, or to enhance the current ones far beyond the planned upgrades.