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17:20
Analog front-end characterization of the RD53A chip
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Natalia Emriskova
(Universite de Strasbourg (FR))
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17:20
GE1/1 Sustained Operations Investigations
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Elizabeth Rose Starling
(Université Libre de Bruxelles (Belgium))
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17:20
The eTx line driver and the eRx line receiver: two building blocks for data and clock transmission using the CLPS standard
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Di Guo
(Southern Methodist University)
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17:20
VMM3a, an ASIC for tracking detectors
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Christos Bakalis
(National Technical Univ. of Athens (GR))
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17:20
The first ASIC prototype of a 28 nm time-space front-end electronics for real-time tracking
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Lorenzo Piccolo
(Politecnico and INFN Torino)
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17:20
ALTIROC2, a readout ASIC for the High Granularity Timing Detector in ATLAS
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Raimon Casanova Mohr
(The Barcelona Institute of Science and Technology (BIST) (ES))
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17:20
A Monitoring 12-bits Fully Differential Second Order Incremental Delta Sigma Converter ADC for TimePIx4
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Raimon Casanova Mohr
(The Barcelona Institute of Science and Technology (BIST) (ES))
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17:20
A Monolithic Active Pixel Sensor for CEPC vertex detector
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Tianya Wu
(IFAE,Spain &CCNU,China)
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17:20
FAST: a front-end readout ASIC for a 30 ps time resolution with 6 pF UFSD sensors
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Federico Fausti
(INFN Torino (IT))
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17:20
Low-power SEE hardening techniques and error rate evaluation in 65nm readout ASICs
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Alessandro Caratelli
(EPFL, CERN)
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17:20
A SiPM Readout Front-end with Fast Pulse Generation and Successive-Approximation Register ADC
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Yuxuan Tang
(University of Houston)
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17:20
A High Speed Programmable Analog-to-Digital Conversion System Based On System in Package
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Ruyi Jin
(Institute of High Energy Physics)
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17:20
The Firmware for the European Spallation Source Cavity Simulator
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Maciek Grzegrzółka
(Institute of Electronic Systems, Warsaw University of Technology)
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17:20
Multi-threaded TCP hardware stack for pixel detector readout on 10 Gigabit Ethernet
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Jie Zhang
(Institute of High Energy Physics, Chinese Academy of Sciences)
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17:20
Readiness of the ATLAS Tile Calorimeter link daughterboard for the High Luminosity LHC era
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Eduardo Valdes Santurio
(Stockholm University (SE))
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17:20
Qualification of the final LHCb VELO electronics
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Edgar Lemos Cid
(IGFAE, Universidade de Santiago de Compostela (ES), CERN)
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17:20
RD53A chip susceptibility to electromagnetic conducted noise
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Alvaro Pradas Luengo
(Aragon Institute of Technology (ES))
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17:20
Control and Monitoring for a serially powered pixel demonstrator for the ATLAS Phase-II upgrade
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Clara Troncon
(Milano Universita e INFN (IT))
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17:20
LpGBT Tester: an FPGA based test system for the lpGBT ASIC
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Julian Maxime Mendez
(CERN)
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17:20
Triple-Modular Redundancy Deployment Optimization in the Sensor Readout System of the CBM Micro Vertex Detector
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Yue ZHAO
(IPHC)
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17:20
Proton-Induced Radiation Effects in MAROC3, a full readout 0.35 µm SiGe ASIC
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Lucian Nicolae Cojocariu
(IFIN-HH (RO))
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17:20
Development of a high bandwidth PCIe card for the ATLAS HL-LHC Upgrade and DUNE experiment
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Kai Chen
(Brookhaven National Laboratory (US))
-
17:20
Innovative and Expandable Physical Implementation Method for High-Speed Triple Modular Redundant Digital Integrated Circuits in Radiation-Hard Designs
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Bjorn Van Bockel
-
17:20
Test results of a Flexible Printed Circuit for the ATLAS High Granularity Timing Detector
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Maria Robles Manzano
(Johannes Gutenberg Universitaet Mainz (DE))
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17:20
A NEW COMPACT ELECTRONICS FOR CALICE SIW CALORIMETER READOUT
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Jimmy Jeglot
(CNRS IN2P3 LAL Orsay)
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17:20
Triggering on electrons, photons, tau leptons, jets and energy sums with the CMS Level-1 trigger
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Santeri Henrikki Laurila
(Helsinki Institute of Physics (FI))
-
17:20
COLDATA Architecture, Design and Verification
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James Hoff
(Fermi National Accelerator Lab. (US))
-
17:20
CATIA: APD readout ASIC for the CMS phase 2 ECAL electronics upgrade
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CMS collaboration CMS collaboration
Olivier Gevin
(Université Paris-Saclay (FR))
-
17:20
The ETROC Project: ASIC development for CMS Endcap Timing Layer (ETL) upgrade
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Tiehui Ted Liu
(Fermi National Accelerator Lab. (US))
-
17:20
The powering concept of the CBM Silicon Tracking System
-
Piotr Koczon
(GSI)
-
17:20
Upgrade of the ATLAS TileCal High Voltage system
-
Agostinho Da Silva Gomes
(LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)
-
17:20
Overview of Electronics Developed by ISE for the European Spallation Source Project
-
Igor Rutkowski
(Institute of Electronic Systems, Warsaw University of Technology, Poland)
-
17:20
A custom FPGA mezzanine card for crosstalk measurements of low-mass cables for the high luminosity upgrade of the ATLAS Pixel detector.
-
Katherine Dunne
(University of California,Santa Cruz (US))
-
17:20
Radiation damage of Silicon Photomultipliers by irradiated fast neutrons
-
Bogdan Topko
(Joint Institute for Nuclear Research)
-
17:20
20 Mrad-TID Effects on Time over Threshold performance of GEMINI chip
-
Luca Mangiagalli
(University of Milano-Bicocca)
-
17:20
The VRP - a Versatile Readout Platform for the nuclear experiments at HIRFL-CSR
-
Chengxin Zhao
(Institute of Modern Physics, CAS)
-
17:20
Design of the Back end card for the JUNO experiment
-
Yifan Yang
(iihe)
-
17:20
Processing of the Liquid Xenon Calorimeter’s Signals for Timing Measurements
-
Leonid Epshteyn
(Budker Institute of Nuclear Physics)
-
17:20
The hardware demonstrator of the Phase II ATLAS Level-0 MDT Trigger processor
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Davide Cieri
(Max-Planck-Institut fur Physik (DE))
-
17:20
EureKA-Maru: an ATCA board for the CMS Phase 2 Tracker Upgrade with centralized slow control and board management solution based on a Zynq Ultrascale+ System-on-Chip
-
Luis Ardila
(KIT-IPE)
-
17:20
New Quench Detection System to Enhance Protection of the Individually Powered Magnets in the Large Hadron Collider
-
Severin Haas
(CERN)
-
17:20
Design of Finite State Machines for SRAM-based FPGAs operated in radiation field
-
Matteo Lupi
(CERN / Johann-Wolfgang-Goethe Univ. (DE))