Conveners
ASIC
- Grzegorz Deptuch (Fermi National Accelerator Lab. (US))
ASIC
- Grzegorz Deptuch (Fermi National Accelerator Lab. (US))
ASIC
- Angelo Rivetti (Universita e INFN Torino (IT))
ASIC
- Angelo Rivetti (Universita e INFN Torino (IT))
ASIC
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
ASIC
- Ping Gui (Southern Methodist University (US))
ASIC
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
ASIC
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
The analog front-end readout electronics of the ATLAS Liquid Argon (LAr) Calorimeter will be replaced by a single chip as part of the upgrades for the High-Luminosity Large Hadron Collider (HL-LHC) program. The cornerstone of the circuit is the very demanding preamplifier, which must have low noise (0.4 nV/√Hz), large dynamic range (up to 10 mA, 16 bits) and precise input impedance (25 or 50...
We present the design and test results of a 4-channel 10-Gbps/ch Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver, the cpVLAD, with on-chip charge pumps to extend the biasing headroom for the VCSEL’s needs for low temperature operation and mitigation of the radiation effects. The cpVLAD was fabricated in a 65-nm CMOS technology. The test results show that the cpVLAD is capable of...
An innovative CGEM (Cylindrical Gas Electron Multiplier) detector will upgrade the current inner tracker of the BESIII experiment.
A custom 64ch ASIC has been specifically designed for the analog readout.
The features of the engineering run version of TIGER will be presented alongside with the ASIC characterization and calibration.
The data are then collected via optical links by two different...
A Clock-Data Recovery (CDR) circuit has been developed to be integrated in the RD53B front end chip for the HL-LHC upgrade of the ATLAS/CMS pixel detector. The 160 Mb/s input data stream is recovered and used to synthesize the 1.28 GHz clock that drives the high speed output link. Robust locking is guaranteed by starting up in PLL mode and afterwards automatically switching to CDR operation....
The Low-Power Gigabit Transceiver (lpGBT) is a radiation tolerant ASIC for multipurpose high-speed bidirectional optical links in HEP experiments. It supports 2.56 Gbps for the downlink and 5.12 or 10.24 Gbps for the uplink. Its data interface to the detectors’ frontends is highly configurable supporting multiple data rates. The lpGBT is a fixed and deterministic latency device that can be...
A prototype chip named RD50-MPW2 in the 150 nm High-Voltage CMOS (HV-CMOS) technology from LFoundry has been designed and submitted for fabrication within the CERN-RD50 collaboration. The chip contains a matrix of depleted CMOS pixels with monolithically integrated readout electronics. The focuses of the chip are on improving the readout speed that is achieved by designing high-speed,...
The high degree of flexibility in the firmware development makes FPGA designs and the development environment vulnerable to errors. Continuous integration is a fast way to detect a majority of such errors. Additionally, simulations and hardware tests can be automated using test methodologies (e.g. unit test). Continuous integration offers the benefits of reproducible results, fast error...
This paper describes the first experimental results from the characterization of the analog front-end designed for the readout of a Si(Li) detector based tracker. The instrument is conceived for the identification of low-energy cosmic-ray antiprotons and antideuterons in the GAPS (General Antiparticle Spectrometer) experiment to search for dark matter, whose launch is currently scheduled for...
We present the ASIC development and test results of the picoTDC, a 64 channel time tagging TDC with 3ps bin size. The ASIC runs from a single 40MHz reference clock, can be configured very flexible, supports hit rates of up to 320MHz per channel, internal buffering and trigger matching as well as TOT measurements. A prototype has been produced in a 65nm CMOS technology and first test results...
ALTIROC1 is a 25-channel ASIC designed to readout the 5 x 5 matrix of 1.3 mm x 1.3 mm x 50 µm Low Gain Avalanche Diodes (LGAD) of the ATLAS HGTD detector. The targeted combined time resolution of the sensor and the readout electronics is 50 ps/hit. Each ASIC channel integrates a RF preamplifier followed by a high speed discriminator and two TDCs for Time-of-Arrival and Time-Over-Threshold...
The CMS Detector will be upgraded for the HL-LHC to include a MIP Timing Detector (MTD). The MTD will consist of barrel and endcap timing layers, BTL and ETL, respectively, providing precision timing of charged particles. The BTL sensors are based on LYSO:Ce scintillation crystals coupled to SiPMs with TOFHIR ASICs for the front-end readout system. A resolution of 30 ps for MIP signals at a...
Here we describe the DECAL Monolithic Active Pixel Sensor (MAPS) for digital electromagnetic calorimetry. The sensor consists of a matrix of 64x64 55um pixels, and provides a readout at 40MHz of the number of particles which have struck the matrix in the preceding 25ns. It can be configured to report this as a total sum across the sensor (equivalent to the pad of an analogue calorimeter) or...
The CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a $180$nm HR-CMOS Imaging Process. The chip, designed in the context of the CLIC tracking detector study, comprises a matrix of ${16\times128}$ detector channels, each measuring ${300\times30}\mu$$m^{2}$. To ensure prompt charge collection, each channel is segmented in eight collection diodes, each containing...
The LF2 is a depleted MAPS prototype chip produced in the LFoundry 150 nm HV-CMOS process on 500 Ωcm and 1900 Ωcm wafers. The chip includes two monolithic matrices. One matrix of 40 rows x 78 columns contains 50 x 50 μm2 pixels each with a charge sensitive amplifier, a shaper, and a discriminator, which are readout by a digital block with FE-I3 column drain architecture. A 26 x 52 photon...
The design and measurement results of different versions of ultra-low power fast 10-bit SAR ADC prototypes, fabricated in CMOS 65 nm technology, are presented. The prototypes use different capacitive DACs, different DAC switching schemes and different asynchronous logic. All prototypes are fully functional, achieving good linearity (with both INL and DNL below 1 LSB) and ENOB around 9.3 for...
SALT is a 128-channel readout ASIC, designed in CMOS 130~nm process, for silicon strip detectors in the upgraded Tracker of LHCb experiment. It extracts and digitises analogue signals from the sensor, performs digital signal processing and transmits serially the output data. SALT uses the innovative architecture comprising of a low power analogue front-end and a 40~MSps 6-bit ADC in each...
The architecture and experimental results for the downlink Equalizer (Eq) and Eye Opening Monitor (EOM) circuits in the lpGBT ASIC are presented. The 2.56 Gbps downlink NRZ data is received by a line receiver that is followed by a Continuous Time Linear Equalizer (CTLE) with programmable transfer function. The EOM circuit scans the output of the Eq with a time resolution of 6.1 ps and a...
This paper presents the design, architecture and experimental results of the ljCDR (Low Jitter CDR) in the lpGBT (Low Power Gigabit Transceiver). The chip includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. The CDR employs a novel loop architecture with a high-speed feed forward loop...
The Low Power GigaBit Transimpedance Amplifier (lpGBTIA) is the optical receiver amplifier in the lpGBT chipset. It is a highly sensitive transimpedance amplifier designed to operate at 2.56 Gbps. It is implemented in a commercial 65 nm CMOS process.
The device has been designed for radiation tolerance and, in particular, to accommodate the radiation effects in photodiodes that manifest...
In this paper, an lpGBT sub-system for environmental monitoring and control of experiments is presented. The monitoring part contains an 8 external and 8 internals inputs followed by a 16-to-1 multiplexer, instrumentation amplifier with selectable gain and a 10-bit ADC. A constant current source can be enabled on each external input to facilitate resistances measurements. Internal channels are...
The design and test results of a multi-channel multi-data rate circuit for phase alignment of data in the lpGBT ASIC fabricated in a 65 nm CMOS technology are presented. The circuit is composed of 4 delay lines regulated by a Delay-Locked Loop followed by logic responsible for phase selection and multi-mode deserializer. The circuit is able to handle up to 4 serial data streams with a data...
