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The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.
LHC experiments (and their operational experience) will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.
The purpose of the workshop is :
- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities
- to review the status of electronics for the LHC experiments
- to identify and encourage common efforts for the development of electronics
- to promote information exchange and collaboration in the relevant engineering and physics communities.
Registration to the workshop and local organisation information are available on:
http://igfae.usc.es/twepp2019/
Organised by the Instituto Galego de Física de Altas Enerxías and Universidade de Santiago de Compostela with support from CERN.
Radiation Physics Laboratory (http://www.usc.es/rpl) is an accredited Secondary Standard Dosimetry Lab in the University of Santiago with more than 10 years of experience on photon and electron TID experiments. Currently the laboratory has a high dose rate 60-Co unit together with an electron linal able to produce 6 MV and 15 MV photon beam qualities and electron beams with 6, 9, 12, 16 and 20 MeV energy. Dose rates at 1 m from focus have a range between 1 Gy/min to 10 Gy/min. The lab works mainly for the aerospace insdustry in the test of components and systems from earth orbit to deep space missions. Additionally at 15 MV photon mode we are able to produce photonuclear neutrons through evaporation process with primary energies around 1 MeV. During the presentation will discuss the conditions to ensure a proper dosimetry evaluation in the irradiation tests.
The new paradigm of Analog to Information Conversion (AIC) aims at extracting information from the environment rather than simply massive amounts of raw data. Focal plane processing is a way of doing so by means of processing the sensed data at the acquisition stage, efficiently reducing bandwidth and power consumption. The use of standard CMOS technologies favours the development of low cost solutions.
Large area photo-detectors with time resolution of the order of 10 ps for low lights levels, down to the single photon, would bring a revolution in many fields. In medical imaging would enable real time PET, in LIDAR would make possible achieving millimetric spatial resolution requiring no averaging and would have a strong impact in other fields as fluorescence imaging and, of course, in high luminosity experiments in particle physics. Although some Microchannel plate photomultipliers (MCP - PMT) may approximate this performance, a solid-state sensor is often preferred. Silicon Photomultipliers (SiPMs) have been able to replace PMTs in many applications as they have significant advantages in some key aspects: higher Photo Detection Efficiency, robustness and insensitivity to magnetic fields. However, application of SiPMs in large area and fast detectors is an open question as the detector capacitance severely degrades performances: lower signal to noise ratio, worse timing resolution, wider pulse shape and therefore higher pile-up. Neither analog nor digital large area SiPMs achieve a Single Photon Time Resolution below 100 ps. We will discuss how detector segmentation can help in this direction and we will present different techniques, ranging from Application Specific Circuits (ASICs) to a proposal for new generation of hybrid photosensors.
The analog front-end readout electronics of the ATLAS Liquid Argon (LAr) Calorimeter will be replaced by a single chip as part of the upgrades for the High-Luminosity Large Hadron Collider (HL-LHC) program. The cornerstone of the circuit is the very demanding preamplifier, which must have low noise (0.4 nV/√Hz), large dynamic range (up to 10 mA, 16 bits) and precise input impedance (25 or 50 Ohms) to terminate the cables from the detector. LAUROC1 is a prototype that integrates an innovative electronically cooled resistor architecture to fulfil these requirements.
The design of the ASIC and testbench measurements will be presented.
We present the design and test results of a 4-channel 10-Gbps/ch Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver, the cpVLAD, with on-chip charge pumps to extend the biasing headroom for the VCSEL’s needs for low temperature operation and mitigation of the radiation effects. The cpVLAD was fabricated in a 65-nm CMOS technology. The test results show that the cpVLAD is capable of driving VCSELs with forward bias voltages as high as 2.8 V. The power consumption of the cpVLAD is 94 mW/ch. Further optical tests and irradiation tests will be carried out and reported at the workshop.
An innovative CGEM (Cylindrical Gas Electron Multiplier) detector will upgrade the current inner tracker of the BESIII experiment.
A custom 64ch ASIC has been specifically designed for the analog readout.
The features of the engineering run version of TIGER will be presented alongside with the ASIC characterization and calibration.
The data are then collected via optical links by two different kind of FPGA-based modules, one in charge to interface the chip and the other deputed to event construction and DAQ communication.
The design of the electronics chain will be presented together with the first results of the integration tests.
We report on the design and performance of the Digitizer ReAdout Controller (DIRAC) of the Mu2e electromagnetic calorimeter, which consists of a 670 CsI crystals matrix readout by SiPM. The 20-channels DIRAC performs 200 MHz sampling of the SiPM signals transmitted by the front-end electronics. Operation in the Mu2e hostile environment expected Total Ionizing Dose (TID) of 12 Krad and neutron fluenceof 5x1010 n/cm2 @ 1 MeVeq (Si)/y, 1T magnetic field, level of vacuum of 10-4 Torr has made the DIRAC design challenging. We describe design, specifications, architecture and results of the performance tests performed on the DIRAC prototypes.
In this contribution, we present the status of the electronics system of the triple-GEM detectors for the CMS GE1/1 upgrade which is being installed in 2019-2020, as well as the performance of ten prototypes which have been operated in CMS during 2017-18. For this new CMS muon sub-detector, a new front-end chip, the VFAT3, has been designed. The VFAT3 communicates with the back-end microTCA electronics through the GBTx chipset and the versatile link. Each of the 144 triple-GEM detectors has 24 VFAT3s, 3 GBTx chipsets as well as a Virtex-6 FPGA. All powered by 9 FEAST DCDC converters.
A four-layer muon telescope has been built employing the equipment and electronics developed for the Top Tracker (TT) detector of the Jiangmen Underground Neutrino Observatory (JUNO). It will serve as a demonstrator of the hardware capabilities in terms of detection efficiency, processing power and system reliability. The entire read out, trigger and acquisition systems have been conceived and build around versatile modular electronics embedding the latest generation of system on chips. A detailed description of the telescope will be given along with the status of the TT electronics and their validation tests.
An overview will be given where we stand with the fundamental questions in particle physics today, and how we
plan to answer these in future with new projects world-wide, either already planned ones or those still under discussion.
The ongoing European Particle Physics Strategy Update process is currently evaluating possible future programs and their physics merits.
This general seminar will show several highlights from the most prominent future projects proposed for both the so called high
energy and high intensity frontier. We’ll look in some detail to the physics questions that these projects will be able to address.
Some of the anticipated new technical challenges will be discussed as well.
A Clock-Data Recovery (CDR) circuit has been developed to be integrated in the RD53B front end chip for the HL-LHC upgrade of the ATLAS/CMS pixel detector. The 160 Mb/s input data stream is recovered and used to synthesize the 1.28 GHz clock that drives the high speed output link. Robust locking is guaranteed by starting up in PLL mode and afterwards automatically switching to CDR operation. Full characterization was performed with the aid of a dedicated test chip. Less than 60 ps p-p jitter was measured while the circuit remains fully functional after a TID of 600 Mrad.
The Low-Power Gigabit Transceiver (lpGBT) is a radiation tolerant ASIC for multipurpose high-speed bidirectional optical links in HEP experiments. It supports 2.56 Gbps for the downlink and 5.12 or 10.24 Gbps for the uplink. Its data interface to the detectors’ frontends is highly configurable supporting multiple data rates. The lpGBT is a fixed and deterministic latency device that can be used for trigger and timing distribution. It features control interfaces and environmental monitoring functions to implement experiment control.
The device was fabricated in a 65 nm CMOS technology. This paper discusses the lpGBT architecture and experimental results.
Mini-MALTA is a Monolithic Active Pixel Sensor prototype developed in the TowerJazz 180 nm CMOS imaging process, with a small collection electrode design (3um), and a small pixel size (36.4 um), on high resistivity substrates and large voltage bias. It targets the outermost layer of the ATLAS ITK Pixel detector for the HL-LHC. This design addresses the pixel in-efficiencies observed in MALTA and TJ-Monopix to meet the radiation hardness requirements. This contribution will present the results from characterisation in particle beam tests that show full efficiency up to 1E15 neq/cm2 and 70 Mrad.
Abstract
Commercial components are used in the readout
electronics of the upgraded ALICE Inner Tracking System detector,
hence a system-level single event upset (SEU) mitigation strategy
for the FPGAs is needed to ensure correct operation. Inclusion of
a flash-based auxiliary FPGA on the Readout Unit enables
fault-tolerant operation, by implementing periodic blind
scrubbing to correct SEUs in the configuration memory of the main
FPGA, an SRAM-based Xilinx FPGA responsible for data transfer and
detector configuration. This contribution discusses the external
scrubber solution on the Readout Unit, focusing on the FPGA
design and software design. Test results are also presented.
A prototype chip named RD50-MPW2 in the 150 nm High-Voltage CMOS (HV-CMOS) technology from LFoundry has been designed and submitted for fabrication within the CERN-RD50 collaboration. The chip contains a matrix of depleted CMOS pixels with monolithically integrated readout electronics. The focuses of the chip are on improving the readout speed that is achieved by designing high-speed, low-noise readout electronics, and minimising the leakage current and increasing the breakdown voltage of the sensor by optimising the chip layout. The design and initial measured results of RD50-MPW2 will be presented in this contribution.
The high degree of flexibility in the firmware development makes FPGA designs and the development environment vulnerable to errors. Continuous integration is a fast way to detect a majority of such errors. Additionally, simulations and hardware tests can be automated using test methodologies (e.g. unit test). Continuous integration offers the benefits of reproducible results, fast error detection, error tracing, avoiding human errors in the build process, and minimizing the manual verification of the firmware. This comes at the price of setting it up with comprehensive integration tools such as GitLab. We present such an integration flow within the CMS experiment.
This paper describes the first experimental results from the characterization of the analog front-end designed for the readout of a Si(Li) detector based tracker. The instrument is conceived for the identification of low-energy cosmic-ray antiprotons and antideuterons in the GAPS (General Antiparticle Spectrometer) experiment to search for dark matter, whose launch is currently scheduled for late 2021. The analog front-end, featuring a dynamic signal compression to comply with the wide input range, has been designed in a 180 nm CMOS technology and was produced in two prototype ASICs. The development will be completed by early summer 2020.
As part of ATLAS Phase-II upgrade project for the High-Luminosity Large Hadron Collider (HL-LHC), an irradiation experiment using a 60Co source was carried out at Brookhaven National Lab to characterize the leakage current from the 130 nm CMOS technology ABCStar chip as a function of the total ionizing dose (TID). The ABCStar chips were held at -10o and 0o C and received dose rates ranging from 0.6 to 2.5 Krad/h. The outcome of the ABCStar irradiation is presented and compared with previous irradiation campaigns utilizing the ABC130 prototype chips, which were irradiated under similar dose rates and temperatures.
The High-Luminosity Large Hadron Collider (HL-LHC) will pose unprecedented requirements in terms of timing distribution. The overall stability has to reach picosecond-levels between tens of thousands of end-points. To mitigate long-term environmental variations in the high-speed optical links, phase monitoring and online/offline compensation might be necessary. The Timing Compensated Link (TCLink) is a protocol-agnostic FPGA core that provides monitoring and picosecond-level phase adjustment capabilities. The features can be customized for different user application requirements. A proof-of-concept of TCLink on a setup composed by a Xilinx FPGA evaluation board, the Versatile Link+ and the lpGBT test chip will be demonstrated.
We will describe a pure clock distribution system, built with discrete RF components, that we
have used to demonstrate the precision that separate clocks generated from a single source can be
distributed within a large detector. Clock signals were distributed directly without any encoding or
clock cleaners (PLLs) through parallel 90m optical ?bers to front-end emulators. The phase noise
measured between two 160 MHz clocks was 0.210 ps/1.0 MHz, integrating between 0.01 Hz and 1
MHz. We will discuss the system, the tests made and the steps we are taking to monitor the clock
stability at the point of distribution.
Recent hardware developments in the experiments and the accelerators, especially for the detector readout electronics for the High-Luminosity LHC, are using FPGAs with embedded processors (SoCs).
This is very popular with HW developers due to the close integration between the computing element running a unix operating system and the programmable logic part of the FPGA. For the HL-LHC, there will be of order two to four thousand such devices across CERN experiments (mainly ATLAS and CMS), posing a number of questions about networking, security, operating system support, scalability of the infrastructures and maintainability. The use cases and the integration aspects were discussed at a workshop held at CERN mid-June 2019.
This talk gives a brief summary of the workshop, the use cases, and the thrust at CERN to find common solutions to the integration aspects and long term support for these types of devices in the experiments and more generally across CERN.
The Versatile Link+ project is about to enter its production phase, ready for the Phase 2 HL-LHC detector upgrades. We present the status of the front-end part of the Versatile Link+ project: the Versatile Link+ Transceiver (VTRx+), which provides a low-mass, radiation tolerant, optical transmit- and receive module for tight integration in the upgrading HL-LHC detectors. We describe the development and thorough testing carried out with the transceiver prototypes and their sub-components and the design decisions that have led to the final production-ready prototype. The planned production timeline, aligned with the assembly timescales of the HL-LHC experiments, is also presented.
The ATLAS Inner Detector will be replaced by an all-silicon system, the
Inner Tracker (ITk) and its innermost part will consist of a pixel detector.
Different silicon sensor
technologies will be employed in its five barrel and endcap layers. Components for structures with multiple modules based
on FE-I4 front-end chips were produced and are in assembly and evaluation.With the arrival of the
first readout chip prototype, the RD53A chip, the development of hybrid detector modules is
starting to address numerous production issues, understanding of which will be crucial for
the layout and production of the final ITk pixel detector modules
We have developed a novel open-source Advanced Telecommunications
Computing Architecture (ATCA) platform - APOLLO - which simplifies the
design of custom ATCA blades by factoring the design into generic
infrastructure and application-specific parts. The APOLLO "Service
Module" provides the required ATCA Intelligent Platform Management
Controller (IPMC), power entry and conditioning, a powerful
system-on-module (SoM) computer, and flexible clock and communications
infrastructure. The APOLLO "Command Module" is customized for the
application but typically includes one or more large
field-programmable gate arrays, several hundred optical fiber
interfaces operating at speeds up to 28 Gbps, memories, and other
supporting infrastructure.
GEMINI is an integrated readout system designed for Triple-GEM detectors. To fully exploit the potential of this technology, GEMINI produces outputs for both arrival time and energy thanks to Time-over-Threshold (ToT) technique. This work presents an analysis of the effect of up-to-20 Mrad-TID absorbed by GEMINI chip in lab environment with X-rays. ToT data analysis before and after irradiation allows estimating overall performance variation while reproducing typical use cases with emulated input signals. Experimental GEMINI rad-hard performance will open new applications for this device.
The ATLAS Inner Detector will be completely replaced by an all silicon tracker for the LHC upgrades in the mid 2020s. The increased resolution and data output rate of the innermost layers of the upgraded detector will require more cables that are low-mass and capable of multi-gigabit transmission.
An FPGA Mezzanine Card (FMC) was developed to interface with an FPGA and a cable bundle to measure crosstalk and bit error rate. We present the design of the cable bundle and the FMC, as well as the firmware used to drive the data and measure bit error rate.
The nEXO project is designed to search for the 0vββ process of 136Xe. It requires high reliability and small volume in the readout electronic system. This research is to improve the integration and the reliability of the circuit. The core chip of the system is a highly integrated programmable chip based on SIP which include two ADC dies and a FPGA die. The complete system is constructed by adding the corresponding circuit, and it has the functions of dual-channel high-speed data sampling, data assembly, communication, and real time data processing.
SAR converters are usually the natural choice to implement monitoring ADCs. Additional circuits for calibration are needed to compensate process variations which become more important for large resolutions and deep-submicron technologies. This paper presents a 12-bits second-order incremental sigma delta converter for TimePix4 fabricated in TSCM 65nm. It does not need calibration and is robust to process variations because most of the signal processing is performed in the digital domain. It provides a maximum conversion rate of 1kHz/s, enough for monitoring the internal signals of the chip, consuming only 8µW. Simulations show a SNR of 84.9dB operating in free-running mode.
The proposed CEPC presents new challenges for the pixel detector in terms of cell size and functionality. A high data rate digital design and readout architecture of a MAPS prototype for the CEPC vertex detector is presented. The column drain based readout architecture, benefiting from the ALPIDE and FE-I3 approach, has been implemented to achieve high spatial resolution, fast readout, and low power consumption. The simulation results indicate the readout logic works properly with the high input data rate of 120MHz; both analogue front end and in-pixel readout logic meet the 25ns bunch spacing.
Ultra-compact electronics is required for the control and readout of the Silicon-Tungsten electromagnetic calorimeter of the future ILD detector (CALICE collaboration). Prototypes have been designed years ago, comprising the ASUs (Active Sensor Units) located inside the detector Slab and housing the front-end ASICs, and an external part for controlling the system and reading out physics data. Up to now, the latter was not to scale with the reduced space and power available at the Slab extremity. The paper will present the new SL-BOARD which has been designed together with a kapton-based interconnection system in order to fit these stringent requirements.
A low-power front-end with on-chip fast pulse generation and customized SAR ADC is developed for SiPM readout design. The on-chip fast pulse generation improves the timing resolution without the need of extra I/O pins. The proposed SAR ADC, reusing the SiPM charge integrator and eliminating the power-hungry charging sensing amplifier, consumes significantly less power compared with conventional solutions. The front-end is designed in a 0.18 μm CMOS technology, achieving a SNDR of 57.53 dB and consumes 3.8 mW of power. The HPF reduces the long-tailed SPE pulse width from 50 ns to 3 ns.
ALTIROC2 is an ASIC designed to readout a pixel matrix of 15 x 15 Low Gain Avalanche Diodes (LGAD) for the High-Granularity Timing Detector in ATLAS. It measures the TOT and TOA with a resolution of tens of ps for each detected hit. Data are temporally stored in a buffer able to cope with latencies up to 35µs. The ASIC also measures the luminosity of each bunch crossing with two different time windows. Timing and luminosity data are transmitted through two high speed e-links at different rates, depending on the radial position of the ASIC in the detector.
For the Phase-2 upgrade of ATLAS and CMS tracking detectors, a new pixel readout chip, with 50x50 um2 pixel pitch, is being designed in 65 nm CMOS technology by the RD53 collaboration. A large-scale demonstrator chip called RD53A, containing design variations in the pixel matrix, among which three different analog front ends, is now available. A dedicated program of testing and detailed characterization has been devised and carried out to qualify the three front ends in terms of key performance parameters for the operation of a pixel detector at HL-LHC.
The CMS electromagnetic calorimeter (ECAL) will be upgraded to maintain detector performance in the challenging environment of the High Luminosity LHC. The front-end readout electronics of the ECAL barrel will be replaced, while maintaining the existing crystals and avalanche photodiodes (APDs). Moreover, the upgrade will optimize the timing resolution of the system. The new front-end electronics consists of two cascading ASICs: a fast, dual gain trans-impedance amplifier (CATIA) and a dual ADC, designed in 130 nm and 65 nm CMOS, respectively. The latest test beam and laboratory test results of CATIA coupled with an ADC will be presented.
COLDATA is the third of three chips designed for operation within the Liquid Argon cryostat of the Deep Underground Neutrino Experiment (DUNE). It is the point-of-contact between the warm, external DUNE DAQ system and the cryogenically-cooled Front-end Boards. All information from warm-to-cold and from cold-to-warm passes through COLDATA. As such, it implements data concentration and frame formation, slow control communication and relay, fast control communication, clock distribution and readout. With so much communication, extensive verification was essential. The following will present the complete COLDATA architecture as well as its unique Verification Plan accomplished following the Universal Verification Methodology.
A serial power scheme will be used for the new inner tracking detector for the Phase-II upgrade of the ATLAS experiment. New elements are required to operate and monitor a serially powered detector, including a detector control system (DCS), constant current sources and front-end electronics with shunt regulators. A demonstrator for the outer barrel is built at CERN to verify the concept and operate multiple serial power chains. This includes all required elements from an interlock system to in-situ monitoring with the new DCS. In this talk we present how serial chains with up to 16 modules can be operated.
For the CERN LHC Run 3, the ALICE experiment completely redesigned the Inner Tracking System, which now consists of seven cylindrical layers instrumented with 24120 Monolithic Active Pixel Sensors, covering an area of $10m^2$.
The ITS is controlled and read out by 192 custom Readout Units, which employ commercial SRAM-based FPGAs and will operate in an ionising radiation field, requiring specific FPGA design to ensure system reliability.
This contribution focuses on the techniques developed for designing radiation tolerant finite state machines, discussing the theoretical background, the actual implementation, and their validation with fault injections and proton irradiation tests.
Jiangmen Underground Neutrino observatory (JUNO) is a neutrino medium baseline experiment constructing in China, with the main goal to determine the neutrino mass hierarchy. A large liquid scintillator volume instrumented by around 20000 large photomultiplier tubes will detect the antineutrinos issued from nuclear reactors.The JUNO electronics system has mainly two parts: the front-end system inside water,the backend system outside water. For the front-end electronics, global control units (GCU) digitize the analog signals and send out event data as well as trigger requests. The BECs are used to collect the trigger requests from GCUs and process for next trigger decision step.
FELIX, the PCIe based framework has been used in the DAQ system of ATLAS Phase-I upgrade and the APA (Anode Plane Assemblies) readout in Single-Phase ProtoDUNE experiment. For the ATLAS HL-LHC upgrade, the fiber optical links from front-ends will have higher speed. This manuscript introduces a FELIX demonstrator board with PCIe interface designed for the HL-LHC upgrade. In this board, 25+ Gbps optical links will be supported with both optical transceivers and FMC+ mezzanine, in addition to FPGA embedded PCIe hard IP block for high bandwidth interface with the CPU.
The Phase-2 CMS tracker back-end processing system is composed by two types of Detector, Trigger, and Control (DTC) boards interfacing the inner and outer tracker, and by the Track Finding Processor (TFP) board performing level-1 track reconstruction from the outer tracker data. Several groups are building hardware to prove key and novel technologies needed in the back-end processing system. EureKA-Maru is designed to contribute to the pool of alternatives a design with an improved thermal performance of the optical transceivers as well as an integrated management solution based on a Zynq Ultrascale+ (US+) System-on-Chip (SoC) device.
The UFSD group of Turin is working at the development of custom front-end electronics for the read-out of thin silicon sensors with moderate internal gain, aiming at high-precision time tagging applications. The development of specific ASIC for timing at INFN-Torino started in 2016. The first two ASIC prototypes, TOFFEE and ABACUS, have been successfully tested in our laboratories and at particle accelerator facilities. Leveraging on the know-how obtained in those two projects, a new low power front-end chip, named FAST, has been designed to reach the intrinsic 30 ps UFSD time resolution with a 6 pF sensor capacitance coupling.
Ten ”slice test” triple-GEM detectors were installed into the CMS endcap in 2017. Data was recorded in 2017-2018, using both cosmic ray muons and LHC collisions. During the slice test, a loss of VFAT2 input channels was observed, with two detectors exhibiting rapidly-increasing channel loss beginning mid-2018.
Concurrent investigations into the cause of the channel loss were launched, one
using the in-situ data from P5, the other seeking to recreate the loss in the controlled setting of an external lab. Results from each investigation, and the steps that were taken to prevent such loss in the future, will be reported.
We present an innovative and expandable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits. The implementation uses a new interleaved placement approach in comparison to a generally used bulk 3-bank constraining method. To optimally constrain the placement of sequential cells as well as combinational cells. The TMR netlist information is used to divide the netlist into banks which do not interact logically and allow SEE charge sharing without compromising reliability. The technique was simulated in a 65 nm CMOS technology and resulted in a reduced total net length of 47 % dynamic power consumption of 25%.
Single Event Effects represent one of the main challenges for digital designs exposed to ionizing particles in high energy physics detectors. Radiation hardening techniques are based on redundancy, leading to a significant increase in power consumption and area overhead. This contribution will present the SEE hardening techniques adopted in the pixel and strip readout ASICs of the PS-modules for the CMS tracker upgrade in relation to power requirements and error rates. Cross-section measurements on the silicon prototypes and expected error-rates evaluated for the CMS tracker particle flux and spectrum will be presented.
The lpGBT transceiver is a radiation tolerant ASIC designed to be used in High Energy Physics detector systems. It aggregates data from up to 28 eLinks to one high-speed link running at 5.12 or 10.24Gbps. In the downlink direction, it can be used for timing and trigger distribution by demultiplexing the incoming downlink bitstream running at 2.56Gbps onto up to 16 eLinks. Moreover, the lpGBT provides additional interfaces to handle the detector slow control. This paper presents the lpGBT tester, based on a Xilinx development kit and a custom FMC card developed to perform the pre-production test.
TCP has been widely used in readout systems. SiTCP is hardware-based TCP stack for Gigabit Ethernet, it realizes direct access and transfer of the data up to 949 Mbps in the memory of FPGA by utilizing TCP communication. The data rate multiplies with the development of pixel detectors for smaller pixels and higher frame-rates. The existing GbE design is no longer satisfied the requirement of transmission bandwidth. This paper describes a multi-threaded TCP hardware stack based on SiTCP for 10 GbE implementing on a single FPGA. The throughput from FPGA to PC is at the upper limits of 10 GbE.
To further improve the existing Quench Detection System (QDS) of individually powered magnets installed in the Large Hadron Collider (LHC), a new radiation tolerant electronic board was developed. The board provides three signal acquisition channels able to acquire with different and configurable signal resolution and acquisition rate the analog signals of different properties.
These enhancements enable the application of different quench detection algorithms depending on the protected magnet. Additionally, the board can be used with newly developed current derivative sensors for reliable detection of symmetric quenches. The board flexibility allows as well using both open and closed loop current sensors.
The Institute of Electronic Systems (ISE) of shall design and deliver hundreds of pieces of various control, signal distribution, and safety modules to be used at the European Spallation Source research facility by the Low-Level RF control, Phase Reference, and Beam Diagnostic systems. This contribution presents the design, as well as strategies and results of acceptance testing of selected modules produced by ISE for the project.
For identification of neutron-antineutron pair production events in the CMD-3 experiment (BINP, Russia) near threshold is necessary to measure the particles flight time in the LXe-calorimeter with accuracy of about 3ns. The duration of charge collection to the anodes is about 5mks, while the required accuracy of measuring of the signal arrival time is less than 1/1000 of that. Besides, the signal shapes differ substantially between events, so the signal arrival time is measured in two stages. To implement that, a developed special electronics performs waveform digitization and OnLine measurement of signals' arrival times and amplitudes.
The MAROC chip was dedicated to MaPMT readout, and its third generation was backup solution in the front-end electronics of the RICH-LHCb Upgrade. Given the expected radiation environment for RICH, the MAROC3 was tested with 35 MeV proton beam at the Nuclear Physics Institute in Juelich, Germany. Investigated samples had the behavior recorded using a dedicated test bench. An increasing in power consumption followed by a rapid annealing - which proceeds at room temperature – was observed. The threshold for TID effects was found between 50 - 100 krad TID (Si), for a TID rate of about 30-170 rad/s.
The Vertex Locator of the LHCb will be upgraded in 2020. As the installation is approaching all the electronics have to be verified and tested. In this poster, the final test setup for all the components and the procedures accomplished will be described. Problems detected and solutions adopted will be explained.
This process goes from visual inspection test of the different boards or bare Asic qualification to a full system test with the final components. The auxiliary boards and specificly designed firmware to properly facilitate the testing will be illustrated.
Silicon Photomultipliers (SiPM) are beginning to be actively used in high-energy physics experiments (CMS, LHCb, ATLAS in CERN), therefore careful study of the effect of high radiation fields on the operation of these devices is necessary. This work studies the effect of irradiation with fast neutrons on the work of SiPM (manufacturing: Hamamatsu Photonics K.K.) with an active area of 1 $mm^2$ (types -010С, -015С, -1325CS) and 9 $mm^2$ (-015P) with the equivalent fluence 1 MeV neutrons in range from $10^{11}$ to $5\cdot10^{14}$ $cm^{-2}$.
The RD53A read-out chip (65 nm CMOS) is a large-scale demonstrator for ATLAS and CMS phase 2 pixel upgrades. It is one of the key elements of the serial powering scheme for the next generation of pixel detectors. The susceptibility of the RD53A chip with respect to external EM noise has an impact on the integration strategies (grounding and shielding schemes) and operating conditions of future Pixel detectors. This paper presents a detailed analysis of the RD53A chip susceptibility to RF conducted disturbances in order to understand and address noise issues of RD53A Chip before the pixel upgrade installation.
The Daughterboard (DB) is the readout link and control board that interfaces the front-end and off-detector electronics for the HL-LHC of the the ATLAS Tile Calorimeter. The DB sends high-speed readout of digitized PMT samples, while receiving and distributing configuration, control and LHC timing. A redundant design, Xilinx SEM, TMR, FEC and CRC strategies minimize single failure points while withstanding single-event upsets and damage from minimum ionizing and hadronic radiation. We present the current results of the performed TID, NIEL and SEU tests, aiming to demonstrate the readiness of the Daughterboard to withstand the radiation requirements imposed by the HL-LHC.
The compact structure of the HGTD proposed for the High Luminosity ATLAS detector upgrade at the CERN LHC requires a design to match the tight mechanical and electrical constraints. Our solution with a flexible printed circuit manages the signals to read out and control the modules, to bias the sensors with high voltage and to power the ASIC. It is crucial to match the characteristic impedance of the lines. The high voltage bias requires clearance and shielding to limit the interference with the digital logic. We present the results of several geometrical and electrical tests performed on the first prototype.
The Endcap Timing Readout Chip (ETROC), being developed for the CMS Endcap Timing Layer (ETL) for HL-LHC, is presented. Each endcap will be instrumented with a two-disk system of MIP-sensitive LGAD silicon devices to be read out by ETROCs for precision timing measurements. The ETROC is designed to handle a 16×16 pixel cell matrix, each pixel cell being 1.3x1.3 mm^2 to match the LGAD sensor pixel size. The design of ETROC, with its unique challenges and how they are addressed, as well as prototype testing results, are presented.
This paper presents the design and test results for the line driver (eTx) and the line receiver (eRx) in the lpGBT, fabricated in 65 nm CMOS technology. The two circuits implement the physical layer of the bi-directional eLink interface of the lpGBT. The eTx is a single-ended-to-differential driver with programmable pre-emphasis and driving current. The eRx is a differential-to-single-ended receiver with programmable line equalization. Both circuits comply with the CERN Low Power Signaling (CLPS) standard and have been qualified for data transmission up to 1.28 Gbps.
The Cavity Simulator reproduces the behavior of superconducting cavities and high power amplifiers used in the medium and high beta sections of European Spallation Source (ESS) linac. The device is foreseen to be used for tests and development of the ESS’s LLRF control system. High-performance Xilinx Kintex Ultrascale FPGA runs dedicated firmware, which performs all calculations including the simulation models. The firmware is also responsible for device control and communication. This contribution presents the general overview of the Cavity Simulator’s firmware together with simulation and measurement results.
A front-end ASIC for 4D tracking is presented. The circuit includes a charge-sensitive amplifier, a discriminator with programmable threshold, and a time-to-digital converter. A prototype has been designed and integrated in 28 nm CMOS technology. The presented design is part of a project aiming at reaching a high resolution both in space and in time, to provide front-end circuitry suitable for next generation colliders.
The first level (L0) muon trigger of the ATLAS experiment will be upgraded to operate at the High Luminosity LHC.
The selectivity of the current L0 muon trigger is limited by the moderate spatial resolution of RPC and TGC. The MDT chambers currently used for precision tracking will be therefore included to improve the momentum resolution and the redundancy.
A hardware demonstrator of the MDT trigger processor is presented. It consists of an ATCA blade, constructed of two separate modules, and based on FPGA technology. An overview of the explored algorithms for the track finding task will also be shown.
The presentation summarizes the powering concept of the Silicon Tracking System for the future CBM experiment at FAIR/Germany. Efficient powering is an important task with the goal to minimize power dissipation and heat development. Also the limited space for power cable routing has to be taken into account. Chosen solutions determine the necessary cooling and cabling effort and therefore have high impact to system integration. Some aspects are already completely solved while other issues have to be further investigated. The current status concerning powering the STS electronics and the subsequent consequences for system integration will be shown.
The Cooling Storage Ring of the Heavy Ion Research Facility in Lanzhou (HIRFL-CSR) is constructed to study nuclear physics and relative applications. The experiments at the HIRFL-CSR drive the development of new detectors. Aiming to reduce the developing time and cost of each detector system, a Versatile Readout Platform (VRP) has been designed as a tentative common readout platform for the detectors at HIRFL-CSR. By adopting the Smartfusion2 FPGA SOC as the main FPGA, the VRP is expected to withstand the radiation environment in the HIRFL-CSR. This paper will discuss the design, implementation and first performance results of the VRP.
Results from the Phase 1 Upgrade of the CMS Level-1 Calorimeter Trigger are presented. The upgrade was completed before the 2016 data-taking and the system served until end of Run II in 2018. The hardware uses Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links and operates in microTCA chassis. Innovations are introduced, such as embedded linux on trigger processing boards and simultaneous eye-scans on data links. The final stage architecture is time-multiplexed. The focus will be on calorimeter trigger algorithm design and their firmware implementation. Precise FPGA floorplanning allows placing of all calorimeter trigger algorithms in a single board.
This paper describes the deployment and optimization process of triple-module redundancy (TMR) under high design constraints against single-event upset (SEU) and single-event transient (SET). It includes modeling of single-event effects (SEE) pulses with TCAD mesh model, TMR deployment strategies, and verification methods. The simulation result shows that the prototype with optimized TMR deployment has high reliability with respect to design requirements. The system can run for more than 5 years without crucial errors. And the equivalent error rate in the working environment is lower than $10^{-9}$.
The High Voltage (HV) system of TileCal, the ATLAS central hadron calorimeter, needs to be upgraded during the so called Phase II Upgrade of the LHC for the HL-LHC. In thw proposed solution, the HV regulation boards are moved away from the detector and deployed in the counting room, safe from radiation damages and with permanent access for maintenance. This option requires a new layout with HV cables about 100 m long, but removes the requirement of radiation hard boards. HV-remote regulation boards have been developed and tested. Preliminary results of the performance will be presented.
The VMM3a is a System on Chip (SoC) custom Application Specific Integrated Circuit (ASIC). It will be used as the front ASIC for both Micromegas and sTGC detectors of the ATLAS Muon New Small Wheels upgrade at CERN. Due to its highly configurable parameters, it has been proposed a variety of tracking detectors and another experiments. It is fabricated in the 130nm Global Foundries 8RF-DM process. The ASIC integrates 64 independently configurable channels each providing amplitude and timing measurements, in digital or analog format. The design aspects and performance of the VMM3a as a production ASIC will be presented.
We present the ASIC development and test results of the picoTDC, a 64 channel time tagging TDC with 3ps bin size. The ASIC runs from a single 40MHz reference clock, can be configured very flexible, supports hit rates of up to 320MHz per channel, internal buffering and trigger matching as well as TOT measurements. A prototype has been produced in a 65nm CMOS technology and first test results show a single-shot RMS resolution better than the bin size (3ps).
ALTIROC1 is a 25-channel ASIC designed to readout the 5 x 5 matrix of 1.3 mm x 1.3 mm x 50 µm Low Gain Avalanche Diodes (LGAD) of the ATLAS HGTD detector. The targeted combined time resolution of the sensor and the readout electronics is 50 ps/hit. Each ASIC channel integrates a RF preamplifier followed by a high speed discriminator and two TDCs for Time-of-Arrival and Time-Over-Threshold measurements as well as a local memory. This front-end must exhibit an extremely low jitter noise while keeping a challenging power consumption of less than 4.5 mW. Detailed measurements will be presented.
The CMS Detector will be upgraded for the HL-LHC to include a MIP Timing Detector (MTD). The MTD will consist of barrel and endcap timing layers, BTL and ETL, respectively, providing precision timing of charged particles. The BTL sensors are based on LYSO:Ce scintillation crystals coupled to SiPMs with TOFHIR ASICs for the front-end readout system. A resolution of 30 ps for MIP signals at a rate of 2.5 Mhit/s per channel is expected at the beginning of HL-LHC operation. We briefly overview the design of the MTD BTL and present first measurements with silicon samples of the TOFHIR ASICs.
We present here the design and performance of the OBDT board, which is the new prototype built to substitute the CMS DT muon on-detector electronics. The OBDT is responsible of the time digitization of the DT signals, allowing further tracking and triggering of the barrel muons. It is also in charge of the slow control tasks of the DT chamber systems. A prototype of this board has been produced and is being tested both in the laboratory and also in test stands with real DT chambers. The full functionality in real conditions is being evaluated, showing very satisfactorily results.
The central building blocks of the ATLAS Strip Tracker Upgrade are the staves and petals which host up to 14 modules per side. The incoming data is sent to the EoS and multiplexed by the lpGBT chips on 10 Gbit/s links and sent via optical transmitters (VL+) off-detector. The EoS is a critical component for the upgrade, sitting at a single-point-of failure location. Prototype boards have been designed, manufactured and tested using the first available lpGBT and VL+ prototypes from CERN. We present the first test results and give an outlook towards the production of 2000 boards using these chips.
For the third running period of the CERN LHC, the ALICE experiment will
undertake several upgrades of its sub-detectors. One of the detectors to be
upgraded is the Inner Tracking System, featuring the new ALPIDE pixel chip.
Control and readout of the 24120 chips are handled by 192 custom FPGA-
based readout units. Each readout unit can forward 9.6Gbps of data to another
custom PCIe card that aggregates the data from several units and transmits it
for further offline/online analysis. Integration and commissioning of the system
is underway and this paper describes the first experiences and results of this
effort.
Today communication protocols (32Gbps PCIE Gen5, 112Gbs PAM4, ...) and FPGAs transceivers speeds are pushing
designer to hardware designs constraints, PCB material choice and layout constraints that where almost never considered years ago.
This presentation is an extract of a CCES technical training, and its purpose is to cover some of the theorical aspects of "high speed",
as well as some tricks and traps to be successfull in those coming designs.
High Density Interconnect hybrids are being developed for the CMS Tracker Phase Two Upgrade for the HL-LHC. These hybrids are flexible circuits with flip-chips, passives and connectors laminated to carbon fibre composite stiffeners. The wirebonding of sensors and the soldering requirements for these components requires an almost perfectly flat surface. A lamination process is proposed, focused on the compatibility with lead-free reflow process. The stack-up of the hybrid was optimized to balance the forces induced by the Coefficient of Thermal Expansion (CTE) differences in the assembly. The proposed lamination process was applied to the 8CBC3 hybrid circuits.
The upgraded CMS tracker at the HL-LHC will feature new silicon modules with a macro-pixel sensor and a strip sensor on top of each other. The modules require three supply voltages (1.0V, 1.2V, 2.5V), which are provided in a two-stage DC-DC conversion powering scheme. Two DC-DC buck converters are supplied in parallel from the first powering stage. A four-layer flexible power hybrid based on the FEAST2 and bPOL2V5 DC-DC converters by CERN has been developed, using custom air-core inductors and a custom shield. The power hybrid development will be presented and the results from the characterization will be discussed.
The first running implementation on FPGA of a histogram-based trigger primitive generator for the CMS Drift Tubes at the HL-LHC is presented. This project is driven by the need to generate a trigger by processing the charge collection times, acquired by means of a TDC, and asynchronously shipped to the back-end. We review the design of the bunch crossing evaluation, its implementation on FPGAs of the Xilinx UltraScale family by means of High-Level Synthesis (HLS), and the performance of a demonstrator board of such a trigger.
The Electron Feature Extractor (eFEX) is one of the core subsystems for the Phase-I upgrade of the ATLAS Level-1 Calorimeter Trigger. In Run 3, the eFEX will identify isolated e/g and tau candidates with much higher discriminatory power than in Run 2. The eFEX subsystem consists of 24 eFEX modules housed in two ATCA shelves. Each eFEX module has up to 200 optical input/output links and more than 400 on-board electrical fan-out links, all running at 11.2Gbps. Four pre-production modules have been made and tested. We present hardware and firmware design experience and test results from the eFEX pre-production modules.
Here we describe the DECAL Monolithic Active Pixel Sensor (MAPS) for digital electromagnetic calorimetry. The sensor consists of a matrix of 64x64 55um pixels, and provides a readout at 40MHz of the number of particles which have struck the matrix in the preceding 25ns. It can be configured to report this as a total sum across the sensor (equivalent to the pad of an analogue calorimeter) or the sum per strip (equivalent to a traditional strip detector). Design and operation of the sensor is described, and the results of chip characterisation are reported and compared to simulations.
The CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a $180$nm HR-CMOS Imaging Process. The chip, designed in the context of the CLIC tracking detector study, comprises a matrix of ${16\times128}$ detector channels, each measuring ${300\times30}\mu$$m^{2}$. To ensure prompt charge collection, each channel is segmented in eight collection diodes, each containing a separate analog front-end. A simultaneous time and energy measurement is performed in the on-channel digital logic. Simulations show a minimum detectable charge of $93e^-$ for $210$mW/cm$^2$ (continuous operation). The main design aspects, as well as the first results from laboratory measurements are presented.
The LF2 is a depleted MAPS prototype chip produced in the LFoundry 150 nm HV-CMOS process on 500 Ωcm and 1900 Ωcm wafers. The chip includes two monolithic matrices. One matrix of 40 rows x 78 columns contains 50 x 50 μm2 pixels each with a charge sensitive amplifier, a shaper, and a discriminator, which are readout by a digital block with FE-I3 column drain architecture. A 26 x 52 photon counter matrix of 75 x 75 μm2 pixels each with a 16-bit counter completes the LF2. Testbench measurements, including charge collection, have been carried out and will be presented.
In view of the High-Luminosity LHC, the Compact Muon Solenoid (CMS) experiment is planning to replace entirely its trigger and data acquisition system. Novel design choices are being explored such as ATCA prototyping platforms and newly available interconnect technologies proving links up to 28 Gb/s. Higher-level trigger object reconstruction is performed through large scale FPGAs (such as Xilinx UltraScale) handling over 50Tb/s of fine granularity detector data with an event rate of 750 kHz. The system design and ongoing hardware R&D will be described.
The luminosity increase of the LHC in Phase-II calls for an in-depth redesign of the entire MDT readout chain. While the high rate of primary detector signals requires increased bandwidth at each level of the data path, the MDT readout must, in addition, supply accurate coordinate information to the trigger system, leading to more reliable identification of high-pT tracks. The pre-selection of muon hits in the presence of large backgrounds from and neutron conversions requires high-speed processing power as well as fast data links, capable to supply the relevant information to the MUCTPi inside the latency of 10 micros
The Belle II Experiment relies on an online level 1 trigger system to reduce the background and achieve the targeted frequency of 30 kHz. Here the basis for all trigger decisions based on data from the Central Drift Camber is the track segment finding. To improve both efficiency and maintainability we restructured the original combinatorial approach to finite state machines. The new implementation is saving about 20 % of FPGA slices. To achieve high test coverage an automated test framework was developed for design time validation. Operational correctness is achieved by integration in cosmic ray tests.
Sub 65-nm technologies can offer to engineers huge advantages for the design of high-density and low power circuits and for the integration of high complexity System-on-Chips. Transistors and gates are almost free for the creative designer, but yet their correct integration requires an exponentially increasing investment in tools and training, and a totally new approach to verification, all the way from the high level system validation to the low-level physical and manufacturing verification. New challenges appear along the design process and have to be consistently addressed by designers and project managers.
First the direct challenges, strongly linked to the technology itself, which are mainly affecting both analog and digital backend flows in multiple aspects: floor-planning, routing, sign-off, power estimation and area reduction. To further complicate this picture, many of these aspects are also subtly intertwined and require often difficult system level decision.
In addition, there are indirect challenges induced by “more than Moore” technologies (e.g. mixed-signal integration and verification), and higher SoC complexity requiring novel functional verification and prototyping methodologies.
This talk will cover in more detail these challenges, focusing mainly around a 28nm technology and will present some of the solutions available to the IC design community. We will also suggest the adoption of some of the most robust design methodology based on existing CAE tools.
The design and measurement results of different versions of ultra-low power fast 10-bit SAR ADC prototypes, fabricated in CMOS 65 nm technology, are presented. The prototypes use different capacitive DACs, different DAC switching schemes and different asynchronous logic. All prototypes are fully functional, achieving good linearity (with both INL and DNL below 1 LSB) and ENOB around 9.3 for sampling rates up to 60-90 MSps, depending on the ADC version. The power consumption is linear with sampling frequency and at 40 MSps it is between 450-600 uW.
SALT is a 128-channel readout ASIC, designed in CMOS 130~nm process, for silicon strip detectors in the upgraded Tracker of LHCb experiment. It extracts and digitises analogue signals from the sensor, performs digital signal processing and transmits serially the output data. SALT uses the innovative architecture comprising of a low power analogue front-end and a 40~MSps 6-bit ADC in each channel. The prototypes of SALT have been already tested confirming full chip functionality and fulfilling expected specifications. The design and results of test measurements will be presented.
The architecture and experimental results for the downlink Equalizer (Eq) and Eye Opening Monitor (EOM) circuits in the lpGBT ASIC are presented. The 2.56 Gbps downlink NRZ data is received by a line receiver that is followed by a Continuous Time Linear Equalizer (CTLE) with programmable transfer function. The EOM circuit scans the output of the Eq with a time resolution of 6.1 ps and a voltage resolution of 40 mV allowing to monitor the quality of the data transmission over the channel. Both circuits have been evaluated and detailed test results will be presented at the conference.
The readout electronics of the CMS electromagnetic calorimeter (ECAL) barrel will be upgraded to meet the Level-1 trigger requirements at HL-LHC. The new very front-end (VFE) electronics will mitigate the increasing noise from the avalanche photodiodes (APDs), discriminate against anomalous APD signals, and provide the extra bandwidth needed to maintain the integrity of the detector signal shape. The front-end (FE) card will provide the streaming of data from VFE to back-end electronics, which will have increased granularity (tower-level to single crystal-level). The design of the full ECAL barrel readout chain and the status of the components R&D will be presented.
The CMS detector will undergo a major upgrade for Phase-2 of the LHC program: the HiLumi LHC, starting around 2026. The Phase-2 CMS back-end electronics will be based on the ATCA standard, with node boards receiving the detector data from the front-ends for processing via custom, radiation-tolerant, optical links. An ATCA hub board, the DAQ and Timing Hub (DTH), will provide the interface between the back-end nodes and the central Trigger, Timing, and DAQ systems. This paper presents the first measurements performed on the initial prototype production, with a focus on clock quality and serial link performance.
The High Luminosity upgrade of the LHC (HL-LHC) is foreseen to increase the instantaneous luminosity by a factor of five over the present LHC nominal value. The resulting, unprecedented requirements for background monitoring and luminosity measurement create the need for new high-precision instrumentation at CMS, using radiation hard detector technologies. This contribution presents a system using the Tracker Endcap Pixel Detector (TEPX) with an additional 75 kHz of dedicated triggers for online measurement of luminosity and beam-induced background. Real-time implementations of algorithms such as pixel cluster counting on an FPGA are explored for online processing of the resulting data.
We present the electrical and radiation characterisation of the production-ready prototype of the bPOL12V DCDC converter, a stacked assembly of two ASICs inside a QFN32 package. The use of a reference voltage generator chip in 130nm CMOS on top of the ASIC integrating the control system and power train enables improved radiation tolerance and the trimming of the output voltage during the production phase. The comparison of results from proton and neutron irradiations evidence that the NIEL hypothesis is not applicable to the LDMOS transistors used for the bPOL12V, hence making the qualification process for displacement damage more complicated.
Radiation- and magnetic field tolerant DCDC converters that step down the voltage from a 2.5V bus are needed for the High-Luminosity detectors. This work presents the developed prototypes, based on ASICs designed in a 130nm CMOS technology. A buck converter (bPOL2V5) is close to production readiness, showing an 89% peak efficiency and tolerance to more than 250Mrad of Total Ionizing Dose and to a fluence of 10^16n/cm^2. The ASIC and the PCB have been co-designed to guarantee high reliability. A lower-volume alternative to bPOL2V5 uses a resonant switched-capacitor architecture and shows comparable efficiency, while employing an eight times smaller inductor.
RD53A is the first prototype of RD53, the pixel detector front-end chip that will be used by the ATLAS and CMS experiments at CERN during HL-LHC, starting operation in 2026. It is implemented using 65 nm technology and it transmits data using up to four lanes running at 1.28 Gbps each. This presentation will describe the implementation of a first readout chain of the RD53A using the ATLAS FELIX card. The readout chain features a third card, called PiLUP, as a protocol converter between RD53A and FELIX, with direct communication planned in future revisions.
A 32 channel, 15ps resolution, Kintex 7 FPGA-based TDC DAQ for time-of-flight and time-over-threshold measurement is demonstrated along with a comparison to previous works. Results include 11ps mean bin size, less than 4ps differential nonlinearity, and less than 10ps of integral nonlinearity. Linearity is improved by multichain averaging with comparison of 1, 2, and 4 chains pre and post-calibration. Implementation difficulties including bubble error, zero length bins, inter-clock region nonlinearity, calibration, chain overflow are discussed with focus on modern FPGA concerns including clock skew and bin realignment. Measurement methods are reviewed as well as a comparison of common TDC methods.
The Inner Tracker silicon strip detector (ITk Strips) a part of the ATLAS upgrade for the HL-LHC. It employs a parallel powering scheme for the bias high voltage and the low voltage power. To reduce the amount of services, on-module DCDC conversion and high voltage switching is required. These features are implemented on the Powerboard using a step-down buck converter (bPOL12V) to drop the low voltage, a GaN FET for the HV switch and a custom ASIC (AMAC) for control and monitoring. This contribution will present the design, initial test results and plans for the production of O(10,000) Powerboards.
As for the High Luminosity LHC the instantaneous luminosity will be increased by a factor 3, an efficient trigger selection will be crucial. To reduce signal latency, the proximity of the readout electronics to the detector becomes very important. A custom designed 63U rack has been chosen as a house for the ATCA based systems allowing installing 50% more shelves in the detector proximity. The higher power dissipation requires an assessment of the impact on the existing underground infrastructures and cooling capabilities verification in a test setup, which also became the cooling facility to qualify the detector boards prototypes.
Serial powering is the baseline option for the pixel detectors in both the ATLAS and the CMS experiment targeting the phase II HL-LHC upgrade. The Shunt-LDO regulator is integrated in the front-end chips to generate the required supply voltages. A new compensation scheme has been developed to operate stable with large Low-ESR load capacitances. A two-stage bandgap voltage reference circuit has been implemented to improve regulation performance. Security features have been added to protect against overvoltage and overload. Additional features have been added to allow regulator operation with small supply currents during the installation phase.
To update associated electronics with fast-timing resistive plate chamber (RPC) detectors, we present here a multi-channel time-tagging module implemented on a low-end and low-power cyclone V FPGA. A key part in each channel has a time-to-digital converter (TDC) in tapped-delay-line (TDL) architecture (built with delay line and associated registers, fine-time encoder, coarse-time counter and look-up-table memory). The firmware implementation employs several techniques, including input-signal reshaping and bubble-noise filtering to deal with GBVS (ground bounce and Vcc sag) effects. It has successfully been tested in all-channel simultaneous operation conditions, with 9.2 to 12.85ps time resolution and full event-detecting efficiency.
The LHC Phase II Upgrade of the ATLAS Tile Calorimeter (TileCal) implies a new readout and trigger architecture. The on-detector readout electronics will transmit detector data to 32 Tile PreProcessor (TilePPr) boards in the counting rooms at the LHC frequency, sending selected data to the ATLAS FELIX and interface with the trigger systems. Each TilePPr is composed of four Compact Processing Modules (CPM) with single-width AMC form factor and one full-size ATCA carrier with 4 slots. This contribution presents the design of the CPMs and first experiences, and reviews the results of the TilePPr prototype for the TileCal Demonstrator programme
For the next upgrade, the ALICE experiment will use a Common Readout Unit (CRU) at the heart of the data acquisition system. The CRU, based on the PCIe40 hardware designed for LHCb, is a common interface between front-ends, computing system and the trigger and timing system. The 475 CRUs will interface 10 different sub-detectors with 3 sub-systems and reduce the total data throughput from 3.5 TB/s to 635 GB/s. The ALICE common firmware framework is under development. It supports data taking in continuous and triggered mode, clock, trigger and slow control delivery. The architecture and results will be presented.
The failure of a first DCDC converter in the power distribution network of the CMS pixel detector system on October 5th, 2017, might have been due to a single failure and did not raise particular concern. However, it was soon followed by a steady rate of failures of DCDCs in random positions in the detector. Projections of this rate to the future led to an ominous scenario where, without resolving interventions, the 2018 data taking would be jeopardised. This talk will report the evolution of the long investigation aimed at uncovering the origin of the problem, to propose temporary patches for the 2018 run and, eventually, a cure to achieve long-term functionality of the power distribution system.
The LHC machine will be upgraded to increase its peak luminosity and possibly reach an integrated luminosity of $3000-4500\;$fb$^{-1}$. The CMS experiment is called for an upgrade to keep up with the new challenges such as unprecedented radiation environment, requiring high resilience, and increased number of events per bunch crossing, requiring higher detector granularity. Consequently, both Outer Tracker (OT) and Inner (IT) Tracker have to fulfill very stringent requirements: OT ($>13000$ independent modules) uses in situ DC/DC converters to parallel distribute 100 kW of power, IT a serial powering scheme to provide about 60 kW among thousands of modular units.
Highly segmented digital tracking calorimeters (DTC) consist of multiple layers of high-granularity pixel detector CMOS sensors and absorption/conversion layers. Two separate prototypes are being developed: (1) an electromagnetic calorimeter (FoCal) for a proposed ALICE upgrade (during LS3) and (2) a hadronic calorimeter for medical proton CT imaging (pCT). These prototypes employ the ALPIDE detector chip developed for the ALICE ITS. The ALPIDEs are mounted on intermediate Aluminum/Polyimide-flexible PCB with ultrasonic welding. This contribution presents findings and solutions to the challenging design of high-speed readout electronics with efficient use of FPGA resources for these prototypes.
We present a 32-channel data acquisition system using the PSEC4A chip and initial applications as a readout system for neutron detectors at Sandia’s Z Pulsed-Power Facility. The PSEC4A is an 8-channel, 10 GSa/s waveform recording ASIC with an analog bandwidth of 1.9 GHz, which also incorporates multi-event buffering to reduce latency induced by close-in-time triggers. In the 32-channel system, four PSEC4As are time synchronized using a common clock delivered from a PLL chip. Triggering can be done using the internal PSEC4A discriminators or via an external input. An optical serial communication link serves as the user interface to the board.
High Voltage-CMOS (HV-CMOS) sensors are the sensor technology of choice for the pixel tracker in the Mu3e experiment at PSI in Switzerland. In this contribution, timing resolution down to 0.5 ns is obtained. Simultaneously, power consumption is held below 28 μW in a pixel size of 60 μm2, enabling 4D tracking in a high-density array. Timing errors due to signal amplitude variations considered special attention to improve time resolution.
The ATLAS experiment will get a new inner tracker (ITk) during the phase II upgrade. The innermost part will be a pixel detector. A new Detector Control System (DCS) is being developed to provide control and monitoring of the ITk pixel detector. The DCS Controller is a CANopen based Application Specific Integrated Circuit foreseen to independently monitor a serial power chain. The final chip is required to be radiation hard up to an ionizing dose of 500 Mrad. In this talk, the functionality of the chip will be discussed and also results from the first test chip will be presented.
A high-density electrode array is being developed for Neutrinoless Double-Beta Decay search in high-pressure gaseous TPC. A sensor, Topmetal-S, is designed to have mm-sized electrode, followed by an amplifier and an ADC based on a 0.35um CMOS process. The Topmetal-S array can collect charge directly without gas avalanche gain to achieve high energy and spatial resolution simultaneously. To realize a ton-scale TPC, approximately one hundred thousand Topmetal-S need to be laid on a meter-sized plane. The greatest challenge is a reliable high-density channels readout. A distributed, self-organizing and fault-tolerance readout network is implemented and will be integrated into the Topmetal-S.
A mixed-signal ASIC developed to readout silicon photomultipliers (SiPM) at low temperature is presented. The chip is designed in a 110 nm CMOS technology. Both single photon counting and Time-over-Threshold (ToT) operating modes are supported. In single photon counting mode an event rate of up to 5 MHz per channel can be accommodated. The time resolution is 50 ps and the target power consumption is less than 5 mW per channel. The architecture of a first 32-channel prototype is described. Dedicated test structures to qualify critical building blocks at cryogenic temperature have also been deployed.
In the 2018 summer the PolarQuEEEst experiment accomplished a measurement
of cosmic rays flux in the Arctic. The detector, installed on a sailboat, was based on
scintillation tiles read by a total of 16 SiPM.
A multi-channel board (called TRB) has been designed to process the discriminated SiPM signals providing self-trigger capability and
time-to-digital conversion. It was based on a Cyclone-V Intel FPGA. TDC
conversion has been implemented in FPGA and in a HPTDC chip (as a backup). The board will be described, main
features and performance will be enlightened and, lastly, future
improvements and potential application will be discussed.
Results of analyzes of Time-of-Arrival measurements with Low-Gain-Avalanche-Diode sensors were carried out for the amplitude or time-over-threshold corrected leading edge measurements and for practical realization of Constant-Fraction-Discrimination based on ideal delay and RC-type low-pass filtering delay. The Expected current waveforms, resulting from modeling of a sensor and application of varied conditioning of a signal in the front-end circuit, including varied transfer functions and their parameters were considered together with practically achievable signal-to-noise ratio. The work has been done to estimate the levels of variations of time-of-arrival measurements that are achievable in the practically built systems.
The design of the Level-0 endcap muon trigger system for the ATLAS experiment at HL-LHC and the status of the development are presented. The new system reconstructs muon candidates with an improved momentum resolution by combining signals from various subdetectors. The trigger efficiency is estimated with Monte-Carlo simulation to be >90%. The trigger rate is also estimated with proton-proton collision data overlaid with one another to account for a pileup condition at
HL-LHC. Track reconstruction hardware based on pattern matching is demonstrated with Virtex UltraScale+ FPGA. The bit error ratio of the data transmission and the power consumption are evaluated.
ATLASPIX3 is a 2cm x 2cm HVCMOS sensor designed to meet the specifications of layer 4, ATLAS inner tracker. ATLASPIX3 is a depleted monolithic CMOS pixel detector. The chip size allows the construction of quad modules of equal size as that of hybrid sensors. ATLASPIX3 supports triggered readout. The hit information is transmitted via 1.28 Gbit/s. The clock, trigger and configuration bits are derived from a single command input that follows RD53 protocol. This contribution will summarize the detector architecture and concentrate on the design of readout circuitry. If available, the first measurement results will be presented.
The detector module of the Silicon Tracking System (STS) of the Compressed Baryonic Matter (CBM) experiment at FAIR (GSI) consists of large double-sided silicon microstrip sensors with a size up to 124 mm x 62 mm. Due to material budget constraints, the sensors are connected to the read-out electronics by long flexible microcables. As the manual assembly of the modules is time-consuming and difficult, a fully customized in-house bonding machine has been developed which allows for a highly automated detector module assembly. We present the bonding machine together with the electrical characterization of the first modules built with it.
LHCb detector is a general purpose experiment instrumented in the forward region
at the LHC, specialized in b- and c- physics, new physics and CP violation. The Vertex
Locator (VELO) detector is being upgraded along with the rest of the tracking system
and readout architecture during 2019-2020. The aim of this poster is to present the
architecture of the control and readout firmware on the VELO specific back-end boards.
Latest progress towards the installation and commissioning will be shown.
SUPIX-1 is the first version of high spatial resolution monolithic active pixel detector prototype led by Shandong University Pixel Group which serves for CEPC tracker system. The chip has 18μm epi-layer with the resistance of 1kΩ·cm using TowerJazz 0.18 μm technology. Each chip has 9 sub-matrices, 64 rows by 16 columns for each matrix, which gives 16 parallel analog outputs with rolling shutter readout mode, and the chip sensitive area is 2mm*7.88mm. The readout system is based on XILINX KC-705 FPGA board with PCI-e data transmission mode.And the pixel sensor gain was calibrated with Fe-55 K-α peak.
CaRIBOu is a flexible data acquisition system for prototyping silicon pixel detectors. The core of the system consists of the Control and Readout (CaR) board, a versatile module providing the hardware environment for various target ASICs, including powering and slow-control infrastructure and high-speed full-duplex GTx links up to 12.5 Gbps. The CaR board connects to a Zynq system-on-chip board, which runs a fully featured Yocto-based Linux and a data acquisition framework (Peary). Using the CaRIBOu system significantly reduces the time required to test and debug detector prototypes by providing ready-to-use peripheries and re-useable software interfaces for a variety of detectors.
Coming developments in X-ray photon sources will increase signal rate and intensity. Similar performance improvements are needed in a new multi-mega pixel imager. Its readout ASIC is to be based on charge-integration, be compatible with different sensor types, include adaptive-gain (to achieve single-photon resolution and high dynamic range), radiation-hard solutions and circuits for rapid characterization. On-chip digital conversion is desirable; readout should happen indefinitely at over 100kfps rate.
It is our intention to present challenges and ideas, to get advantage of the expertise of the HEP community to look for solutions that could be applied to the Photon Science field.
We will present the design and the performance of two drivers in 65 nm TSMC technology, for Silicon Photonics Mach-Zehnder Modulator (MZM) devices, able to withstand radiation levels of up few 1016 n/cm2 and ~0.5 - 1 Grad. The drivers use a CML architecture and are optimized for >500 Mrad and a target a bit rate between 5 to 10 Gbps. They have been tested up to 800 Mrad showing about 25% degradation in voltage. Results of irradiation with ions will been shown. Finally, the results of operations with MZM and Ring-Resonators will be given and discuss the photonic-electronic integration.
This work is concerned with the design and the characterization of digital-to-analog current converters, developed in a 65 nm CMOS technology, conceived for threshold tuning of front-end channels at the HL-LHC experiment upgrades.
Two DAC structures were integrated in a small prototype chip, that was submitted in August 2018 in the framework of the RD53 developments. The prototype has been tested before and after exposure to X-rays up to a TID of 460 Mrad(SiO$_2$).
The main performance parameters of the two structures will be compared and discussed in the conference paper.
This paper presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 4 ps, fabricated in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. To achieve the low resolution, the delay elements are implemented using a new interlocked interpolation technique to reduce the Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) error. The delay line is placed inside a Delay Locked Look (DLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation.
The pixel-strip modules for the CMS Tracker Phase Two Upgrade for the HL-LHC integrate a readout hybrid (PS-ROH) for the control and data acquisition link. This hybrid is based on the new, low power and compact gigabit transceiver (lpGBT) and the Versatile Transceiver VTRx+ specifically designed for the upgrade. A characterization board was first designed to qualify the design rules and the achievable timing performance of the gigabit block. This design enabled the development of the PS-ROH hybrid for the CMS Tracker PS modules. A testing setup was also developed to verify the PS-ROH performance before its integration in modules.
Xilinx Zynq SoCs are used by the CMS TDAQ in its back-end electronics since LHC Run-2, between 2015-2018. For the Phase 2 upgrade of the LHC, about 1000 devices will be deployed, comparable to the number of High Level Trigger (HLT) nodes today. This scale presents challenges for the SoC integration in the experiment network, system administration, network management, booting process and root file system management among others. We present an evaluation of various Linux distributions (PetaLinux, Yocto, ArchLinux, CentOS) and a proposal of how to address the challenges involved in developing and maintaining custom linux distributions for CMS.
During the current major LHC shutdown (2019-2021), the ATLAS experiment at CERN is moving to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX functions as a router between custom serial links and a commodity switch network, which uses industry-standard technologies to communicate with data collection and processing components. This presentation will describe the FELIX system design as well as report on the installation and commissioning of the full system in summer 2019.
In this work, we present a customized pn depletion type Mach-Zehnder modulator (MZM) as well as a fully integrated wavelength division multiplexing (WDM) transmitter design with the merits of high bandwidth and radiation hardness, aiming to upgrade the optical data transmission of future detector systems. A detailed characterization of the modulators on modulation efficiency and RF response was carried out. Based on this work, the first optical link with a data rate of 11.3 Gb/s was set up transmitting 6x10$^{12}$ bits error free.
The Concentrator Integrated Circuit ASIC is a front-end chip for both Pixel-Strip and Strip-Strip modules of the future Phase-2 CMS Outer Tracker upgrade. It collects the digital data coming from eight upstream front-end chips, formats the signal in data packets containing the trigger information from eight bunch crossings and the raw data from events passing the first trigger level, and finally transmits them to the LpGBT unit. A first prototype in a 65nm CMOS technology integrating all functionalities for system level operation, CIC1, has been tested in early 2019. The design and its implementation, along with test results, are presented.
The upcoming upgrade of the readout system of the ATLAS experiment at the LHC at CERN is based on the Front-End LInk eXchange (FELIX) system. As part of this upgrade, approximately 120 custom PCIe cards are being produced by an industrial partner, based on a hardware design developed within the collaboration. Such a large production requires detailed Quality Assurance/Quality Control procedures (QA/QC) to ensure the hardware being produced is fully functional and robust.
For the Long Shutdown 2 upgrade of the ALICE experiment, a new Inner Tracking System (ITS) is under development, based on the ALPIDE Monolitihic Active Pixel Sensor (MAPS) chip.
Data readout from the ALPIDE chips is performed by 192 Readout Units (RU), which are also responsible for trigger distribution, monitoring, configuration, and control of the sensor chips. Monitoring and control of the experiment is performed by the Detector Control System (DCS), normally via optical GBT links offered by the RU. A CANbus interface is also provided as a backup and this paper will discuss the implementation of this interface.
KARATE (KArlsruher high RAte TEst) is a new system to stress the readout chain of strip modules for the future CMS Outer Tracker at HL LHC. The readout chain of a module starts with CMS Binary Chips (CBC) connected simultaneously to two sensors. The sparsified output is send out via an optical link. KARATE injects patterns with varying pulse heights, occupancies and trigger rates into the CBC giving full control on 48 channels at 40 MHz. Afterwards injection pattern are compared with readout patterns. The talk introduces the system and summarizes measurements on a CBC that is read out electrically.
Multimode interferometers (MMI) are key components for high-bandwidth transceivers in upgrading the data transmission of future detector systems. We present 2 conventional high-performance MMIs fabricated on a 250nm SOI platform with different splitting ratios which operate as 50:50 power splitter for Mach-Zehnder modulators and as 86:14 power splitter for loop control in future transceiver designs, respectively. Besides, we present novel MMIs based on sub-wavelength gratings. By engineering the refractive index of relevant sections with sub-wavelength structures, fabricating many-port MMIs with low phase error becomes feasible and also the on-chip footprint of 50:50 MMIs can be decreased dramatically.
We successfully developed, built and tested a low power and stand alone DAQ system to be used with RPCs to measure the muonic component of air showers in the framework of MARTA. The MARTA system includes a front-end readout, high voltage, detector monitoring and a central unit to manage the different components of the system. The front-end is based on the MAROC ASIC coupled to an FPGA respecting the strict demands of field operations in Cosmic Ray experiments. Prototypes were produced and deployed, performing as expected. An engineering array will be installed at the Pierre Auger Observatory.
In this article we describe the measurement results on an “AARDVARC” prototype in 130 nm. AARDVARC is a multi-channel waveform digitizing and processing Application Specific Integrated Circuit (ASIC) front-end. We report on various performance metrics: fast sampling (10-14 Gsa/s), deep storage (32K samples), timing resolution (better than 5ps), low power consumption (<100mW/channel).
Reliable measurement of clock signal parameters is important in precise-timing applications. Such parameters include frequency, phase, duty cycle and channel-to-channel skew. Especially in applications in which test time for multiple channels is a significant factor, efficient parallelization of measurements is crucial, while often coming with significant extra cost. This work presents an approach to characterizing clock signal parameters using off-the-shelf FPGA evaluation hardware.
Approaches for both static measurements (steady-state behaviour) as well as dynamic measurements are presented. Both presented measurement concepts are applied in practice and their achieved performance is presented.
The KINTEX-7 FPGA is to be used in the new digital readout of the upgraded LHCb-RICH sub-detectors. This summary presents the measurements done to evaluate the reliability of this FPGA under ionizing radiation exposure with different types of particle beams: ions, protons and X-rays. Single-event effect cross-sections for critical resources - such as Flip-Flops, RAM blocks, configuration memory, and I/O blocks - have been evaluated for multiple values of total ionizing dose, linear energy transfer, proton energy, and particle flux. A list of firmware constrains for this RICH application was deduced based on extrapolation to upgraded LHCb and 50 fb-1.
Triple-GEM has been adopted for the GE2/1 upgrade of the forward muon detector at CMS for the High Luminosity LHC. GE2/1 chambers are segmented in 4 modules. Each module is equipped with the Optohybrid (OH) interfaced to 12 VFAT3 ASICs. The OH uses GBTs for the readout path and is equipped with a Xilinx Artix-7 FPGA for the trigger data processing.
In this presentation we report on our initial developments of the GE2/1 electronics.
We also discuss the hardware, firmware and software developments, results of measurements with the first
demonstrator and outline our production plans.
Modern VLSI technology allows the development of new class X-ray imaging detectors capable of capturing an image in various energy ranges in one shot. Such spectroscopic imaging detectors have a high demand for the spatial and energy resolution of individual photons. With decreasing size of pixels, the charge cloud generated by the primary photon interaction, and in high-Z materials also by the fluorescent photon interaction, is shared across several pixels. That limits both spatial and spectroscopy resolution. This paper presents a novel charge summing algorithm called Winner-Master-Slave and describes the functionality, implementation, and simulation of the proposed algorithm in Verilog-AMS.
The CMS Outer Tracker at HL-LHC will have to cope with 300 pile-up events per bunch crossing and to improved tracking performance while operating at a trigger rate up to $\mathrm{1~MHz}$. The front-end electronics readout chain consists of sensor readout ASICs connected to a data concentrator ASIC featuring zero-suppression. This contribution presents the methodology and the analysis work for the sizing of a multichip FIFO-based architecture and implementation of a full exception handling mechanism featuring a robust data readout synchronization and event loss probability lower than $\mathrm{0.1\%}$ at the highest pile-up condition with a power density lower than $\mathrm{100~mW/{cm^2}}$.
At INFN-Torino, ASICs for readout applications of detectors were designed in several technologies, and are now under development. The 110 nm CMOS UMC technology is applied too. This technology has been chosen for its lower cost with respect to IBM or TSMC, even if there was not a systematic characterization for what concerns the radiation tolerance. Obviously, it is important to know the behavior of this technology under radiation. For this reason, configuration registers of a full size prototype for the custom readout circuit of silicon double-sided microstrips of PANDA Micro Vertex Detector were tested with ion and proton beams.
The COMET detector will include a electromagnetic calorimeter (ECal). The ECal signals will used for energy deposition measurement and for triggering. For triggering, the calorimeters signals will transformed into special short-shaped analog signals. These signals will then digitally processed with special algorithm, which allows one to obtain a set of logic signals necessary for event selection and a time-tag signal for time alignment of time measurements.
The final design and performance of the front-end and trigger electronics of the electromagnetic calorimeter of the COMET experiment will be presented.
The Compressed Baryonic Matter experiment (CBM) will study rare probes in a heavy-ion environment at high interaction rates of up to 10 MHz. The observation of detached vertices requires a topological trigger, which is realized in software. CBM opted for a free-running readout, for reasons similar to LHC-b. The primary beam is delivered by a slow extraction synchrotron. To be able to operate the experiment at highest interaction rates, despite beam intensity fluctuations, a time-based throttling mechanism is under study. We will compare different throttling strategies.
VICE++ is a FPGA-based unit with interfaces compatible with the upgrade Very
Front End (VFE) and Front End (FE) boards. Once equipped with the appropriate firmware, it act as a test unit for debugging and tuning of different versions
of VFE and FE prototypes, and as a building block of the QC/QA systems for VFE and FE production. FPGA power allow run lpGBT-FPGA firmware, hence the unit can emulate some functionality of the on-detector electronics for the off-detector electronics tests. The board can be used to evaluate the quality of the data transactions from the FE to the Back-End electronics.
We present tests with a scanning micro-focus photon beam of the miniMALTA DMAPS prototype developed for ATLAS ITk. Tests were carried out at Diamond Light Source which provided a 2um beamspot to be scanned in 1um steps. This allows the in pixel efficiency to be measured directly with high statistics. Three pixel design variations were measured, the standard design, a deeper p well design and an n gap design. This was repeated for an unirradiated chip, a neutron irradiated device and three proton irradiated samples. We compare the effect of different levels of radiation damage on the different pixel designs.
This paper presents the design, architecture and experimental results of the ljCDR (Low Jitter CDR) in the lpGBT (Low Power Gigabit Transceiver). The chip includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. The CDR employs a novel loop architecture with a high-speed feed forward loop stabilization. The circuit was fabricated in a 65 nm CMOS technology and has been tested experimentally with heavy ions from 10.0 MeV.cm²/mg up to 62.5 MeV.cm²/mg.
The Low Power GigaBit Transimpedance Amplifier (lpGBTIA) is the optical receiver amplifier in the lpGBT chipset. It is a highly sensitive transimpedance amplifier designed to operate at 2.56 Gbps. It is implemented in a commercial 65 nm CMOS process.
The device has been designed for radiation tolerance and, in particular, to accommodate the radiation effects in photodiodes that manifest themselves as an increase of both their dark current and junction capacitance. The operation of the lpGBTIA was successfully tested and this paper describes its architecture, the experimental and irradiation results.
In this paper, an lpGBT sub-system for environmental monitoring and control of experiments is presented. The monitoring part contains an 8 external and 8 internals inputs followed by a 16-to-1 multiplexer, instrumentation amplifier with selectable gain and a 10-bit ADC. A constant current source can be enabled on each external input to facilitate resistances measurements. Internal channels are used to monitor power supplies and the output of the temperature sensor. The control part includes a precise 1V voltage reference and a 12-bit voltage DAC. All the blocks were prototyped in 65nm CMOS technology, fully characterized and measurement results are presented.
More than twenty-five thousand hybrids will be produced for the CMS Tracker Phase Two
Upgrade. The hybrids are assembled with flip-chips, passives and carbon-fibre stiffeners. They will
be glued to their module supports, together with powering and optical transmission hybrids,
making repairs almost impossible. Due to the complexity of the hybrid circuits and the circuit
assembly, production scale testing is a very important aspect. A crate-based scalable test system
was designed to enable a multiplexed test of front-end hybrids. A test card was produced for the 2S
hybrids and two different hybrid test cards are under development.
A major upgrade of the ALICE Detector is underway during LHC LS2 (2019-2020). This includes a new Inner Tracking System (ITS) consisting of seven cylindrical layers of CMOS Monolithic Active Pixel Sensors. The building blocks of each layer are azimuthal elements called Staves.
The Inner Layer Staves are made of a carbon fiber support structure (spaceframe), a carbon fiber cold plate and a Hybrid Integrated Circuit (HIC) consisting of Pixel Chips and passive components bonded onto an aluminum polyimide Flexible Printed Circuit (FPC).
This contribution will describe the Inner Layers Staves, the manufacturing processes and the quality assurance methodologies.
CMS is planning to install GEM chambers as part of the Muon upgrade for High Luminosity Operation at the LHC. The front-end ASIC (VFAT3) has been produced in volume together with its hybrid PCB. This paper describes the design of a custom test bench for the production Quality Control (QC) of the VFAT3 hybrids. The full QC procedure incorporates calibration and performance measurements, database entries and statistical data analysis. The paper details the optimization of firmware and software functions reducing the test time per hybrid from 30 to 1.2 minutes. Pre-Series production of 1000 hybrids shows a yield of 94%.
September 2019 marks 20 years since the signature of the Medipix2 Collaboration agreement. Since then 3 generations of pixel detector readout chips have been or are being developed: Medipix2 and Timepix (with recently the addition of Timepix2), Medipix3 and Timepix3 and finally Medipix4 and Timepix4. The Medipix chips have sought to provide high-rate spectroscopic photon counting with hit-by-hit on-pixel energy binning. The Timepix chips, on the other hand, aim to transmit as much hit information as possible off-chip (pixel coordinates, arrival time, time-over threshold). The chip architectures and some of the design choices made will be described. Of course, in spite of our best efforts, we have faced and overcome significant technical challenges over the years and some of these will be discussed. Finally, a large number of applications – both foreseen and unforeseen, within and beyond high energy physics – have been addressed and a selection of those will be described.
The design and test results of a multi-channel multi-data rate circuit for phase alignment of data in the lpGBT ASIC fabricated in a 65 nm CMOS technology are presented. The circuit is composed of 4 delay lines regulated by a Delay-Locked Loop followed by logic responsible for phase selection and multi-mode deserializer. The circuit is able to handle up to 4 serial data streams with a data rate of 160, 320, 640, or 1280 Mbit/s. The test results show that all blocks are functional in all modes of operation.
The new LHCb Vertex Locator for LHCb, comprising a new pixel detector and readout electronics will be installed in 2020 for data-taking in Run 3 at the LHC. The electronics centre around the "VeloPix" ASIC at the front-end operating in a triggerless readout at 40$\,$MHz. Custom serialisers send zero-suppressed data from the VeloPix at a line rate of 5.13$\,$Gb/s. Signal integrity tests of the data path components showing characteristic impedance and jitter measurements will be presented. System tests of the complete electronic and optical chain, along with early results from the VELO module production sites will be shown.