Radiation Physics Laboratory (http://www.usc.es/rpl) is an accredited Secondary Standard Dosimetry Lab in the University of Santiago with more than 10 years of experience on photon and electron TID experiments. Currently the laboratory has a high dose rate 60-Co unit together with an electron linal able to produce 6 MV and 15 MV photon beam qualities and electron beams with 6, 9, 12, 16 and 20...
The new paradigm of Analog to Information Conversion (AIC) aims at extracting information from the environment rather than simply massive amounts of raw data. Focal plane processing is a way of doing so by means of processing the sensed data at the acquisition stage, efficiently reducing bandwidth and power consumption. The use of standard CMOS technologies favours the development of low cost...
Large area photo-detectors with time resolution of the order of 10 ps for low lights levels, down to the single photon, would bring a revolution in many fields. In medical imaging would enable real time PET, in LIDAR would make possible achieving millimetric spatial resolution requiring no averaging and would have a strong impact in other fields as fluorescence imaging and, of course, in high...
The analog front-end readout electronics of the ATLAS Liquid Argon (LAr) Calorimeter will be replaced by a single chip as part of the upgrades for the High-Luminosity Large Hadron Collider (HL-LHC) program. The cornerstone of the circuit is the very demanding preamplifier, which must have low noise (0.4 nV/√Hz), large dynamic range (up to 10 mA, 16 bits) and precise input impedance (25 or 50...
We report on the design and performance of the Digitizer ReAdout Controller (DIRAC) of the Mu2e electromagnetic calorimeter, which consists of a 670 CsI crystals matrix readout by SiPM. The 20-channels DIRAC performs 200 MHz sampling of the SiPM signals transmitted by the front-end electronics. Operation in the Mu2e hostile environment expected Total Ionizing Dose (TID) of 12 Krad and neutron...
We present the design and test results of a 4-channel 10-Gbps/ch Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver, the cpVLAD, with on-chip charge pumps to extend the biasing headroom for the VCSEL’s needs for low temperature operation and mitigation of the radiation effects. The cpVLAD was fabricated in a 65-nm CMOS technology. The test results show that the cpVLAD is capable of...
In this contribution, we present the status of the electronics system of the triple-GEM detectors for the CMS GE1/1 upgrade which is being installed in 2019-2020, as well as the performance of ten prototypes which have been operated in CMS during 2017-18. For this new CMS muon sub-detector, a new front-end chip, the VFAT3, has been designed. The VFAT3 communicates with the back-end microTCA...
A four-layer muon telescope has been built employing the equipment and electronics developed for the Top Tracker (TT) detector of the Jiangmen Underground Neutrino Observatory (JUNO). It will serve as a demonstrator of the hardware capabilities in terms of detection efficiency, processing power and system reliability. The entire read out, trigger and acquisition systems have been conceived and...
An innovative CGEM (Cylindrical Gas Electron Multiplier) detector will upgrade the current inner tracker of the BESIII experiment.
A custom 64ch ASIC has been specifically designed for the analog readout.
The features of the engineering run version of TIGER will be presented alongside with the ASIC characterization and calibration.
The data are then collected via optical links by two different...
An overview will be given where we stand with the fundamental questions in particle physics today, and how we
plan to answer these in future with new projects world-wide, either already planned ones or those still under discussion.
The ongoing European Particle Physics Strategy Update process is currently evaluating possible future programs and their physics merits.
This general seminar...
A Clock-Data Recovery (CDR) circuit has been developed to be integrated in the RD53B front end chip for the HL-LHC upgrade of the ATLAS/CMS pixel detector. The 160 Mb/s input data stream is recovered and used to synthesize the 1.28 GHz clock that drives the high speed output link. Robust locking is guaranteed by starting up in PLL mode and afterwards automatically switching to CDR operation....
Abstract
Commercial components are used in the readout
electronics of the upgraded ALICE Inner Tracking System detector,
hence a system-level single event upset (SEU) mitigation strategy
for the FPGAs is needed to ensure correct operation. Inclusion of
a flash-based auxiliary FPGA on the Readout Unit enables
fault-tolerant operation, by implementing periodic blind
scrubbing to correct SEUs in...
A prototype chip named RD50-MPW2 in the 150 nm High-Voltage CMOS (HV-CMOS) technology from LFoundry has been designed and submitted for fabrication within the CERN-RD50 collaboration. The chip contains a matrix of depleted CMOS pixels with monolithically integrated readout electronics. The focuses of the chip are on improving the readout speed that is achieved by designing high-speed,...
As part of ATLAS Phase-II upgrade project for the High-Luminosity Large Hadron Collider (HL-LHC), an irradiation experiment using a 60Co source was carried out at Brookhaven National Lab to characterize the leakage current from the 130 nm CMOS technology ABCStar chip as a function of the total ionizing dose (TID). The ABCStar chips were held at -10o and 0o C and received dose rates ranging...
The high degree of flexibility in the firmware development makes FPGA designs and the development environment vulnerable to errors. Continuous integration is a fast way to detect a majority of such errors. Additionally, simulations and hardware tests can be automated using test methodologies (e.g. unit test). Continuous integration offers the benefits of reproducible results, fast error...
The High-Luminosity Large Hadron Collider (HL-LHC) will pose unprecedented requirements in terms of timing distribution. The overall stability has to reach picosecond-levels between tens of thousands of end-points. To mitigate long-term environmental variations in the high-speed optical links, phase monitoring and online/offline compensation might be necessary. The Timing Compensated Link...
We will describe a pure clock distribution system, built with discrete RF components, that we
have used to demonstrate the precision that separate clocks generated from a single source can be
distributed within a large detector. Clock signals were distributed directly without any encoding or
clock cleaners (PLLs) through parallel 90m optical ?bers to front-end emulators. The phase...
This paper describes the first experimental results from the characterization of the analog front-end designed for the readout of a Si(Li) detector based tracker. The instrument is conceived for the identification of low-energy cosmic-ray antiprotons and antideuterons in the GAPS (General Antiparticle Spectrometer) experiment to search for dark matter, whose launch is currently scheduled for...
The ATLAS Inner Detector will be replaced by an all-silicon system, the
Inner Tracker (ITk) and its innermost part will consist of a pixel detector.
Different silicon sensor
technologies will be employed in its five barrel and endcap layers. Components for structures with multiple modules based
on FE-I4 front-end chips were produced and are in assembly and evaluation.With the arrival of...
We have developed a novel open-source Advanced Telecommunications
Computing Architecture (ATCA) platform - APOLLO - which simplifies the
design of custom ATCA blades by factoring the design into generic
infrastructure and application-specific parts. The APOLLO "Service
Module" provides the required ATCA Intelligent Platform Management
Controller (IPMC), power entry and conditioning, a...
GEMINI is an integrated readout system designed for Triple-GEM detectors. To fully exploit the potential of this technology, GEMINI produces outputs for both arrival time and energy thanks to Time-over-Threshold (ToT) technique. This work presents an analysis of the effect of up-to-20 Mrad-TID absorbed by GEMINI chip in lab environment with X-rays. ToT data analysis before and after...
The ATLAS Inner Detector will be completely replaced by an all silicon tracker for the LHC upgrades in the mid 2020s. The increased resolution and data output rate of the innermost layers of the upgraded detector will require more cables that are low-mass and capable of multi-gigabit transmission.
An FPGA Mezzanine Card (FMC) was developed to interface with an FPGA and a cable bundle to...
The nEXO project is designed to search for the 0vββ process of 136Xe. It requires high reliability and small volume in the readout electronic system. This research is to improve the integration and the reliability of the circuit. The core chip of the system is a highly integrated programmable chip based on SIP which include two ADC dies and a FPGA die. The complete system is constructed by...
SAR converters are usually the natural choice to implement monitoring ADCs. Additional circuits for calibration are needed to compensate process variations which become more important for large resolutions and deep-submicron technologies. This paper presents a 12-bits second-order incremental sigma delta converter for TimePix4 fabricated in TSCM 65nm. It does not need calibration and is robust...
The proposed CEPC presents new challenges for the pixel detector in terms of cell size and functionality. A high data rate digital design and readout architecture of a MAPS prototype for the CEPC vertex detector is presented. The column drain based readout architecture, benefiting from the ALPIDE and FE-I3 approach, has been implemented to achieve high spatial resolution, fast readout, and low...
Ultra-compact electronics is required for the control and readout of the Silicon-Tungsten electromagnetic calorimeter of the future ILD detector (CALICE collaboration). Prototypes have been designed years ago, comprising the ASUs (Active Sensor Units) located inside the detector Slab and housing the front-end ASICs, and an external part for controlling the system and reading out physics data....
A low-power front-end with on-chip fast pulse generation and customized SAR ADC is developed for SiPM readout design. The on-chip fast pulse generation improves the timing resolution without the need of extra I/O pins. The proposed SAR ADC, reusing the SiPM charge integrator and eliminating the power-hungry charging sensing amplifier, consumes significantly less power compared with...
ALTIROC2 is an ASIC designed to readout a pixel matrix of 15 x 15 Low Gain Avalanche Diodes (LGAD) for the High-Granularity Timing Detector in ATLAS. It measures the TOT and TOA with a resolution of tens of ps for each detected hit. Data are temporally stored in a buffer able to cope with latencies up to 35µs. The ASIC also measures the luminosity of each bunch crossing with two different time...
For the Phase-2 upgrade of ATLAS and CMS tracking detectors, a new pixel readout chip, with 50x50 um2 pixel pitch, is being designed in 65 nm CMOS technology by the RD53 collaboration. A large-scale demonstrator chip called RD53A, containing design variations in the pixel matrix, among which three different analog front ends, is now available. A dedicated program of testing and detailed...
The CMS electromagnetic calorimeter (ECAL) will be upgraded to maintain detector performance in the challenging environment of the High Luminosity LHC. The front-end readout electronics of the ECAL barrel will be replaced, while maintaining the existing crystals and avalanche photodiodes (APDs). Moreover, the upgrade will optimize the timing resolution of the system. The new front-end...
COLDATA is the third of three chips designed for operation within the Liquid Argon cryostat of the Deep Underground Neutrino Experiment (DUNE). It is the point-of-contact between the warm, external DUNE DAQ system and the cryogenically-cooled Front-end Boards. All information from warm-to-cold and from cold-to-warm passes through COLDATA. As such, it implements data concentration and frame...
A serial power scheme will be used for the new inner tracking detector for the Phase-II upgrade of the ATLAS experiment. New elements are required to operate and monitor a serially powered detector, including a detector control system (DCS), constant current sources and front-end electronics with shunt regulators. A demonstrator for the outer barrel is built at CERN to verify the concept and...
For the CERN LHC Run 3, the ALICE experiment completely redesigned the Inner Tracking System, which now consists of seven cylindrical layers instrumented with 24120 Monolithic Active Pixel Sensors, covering an area of $10m^2$.
The ITS is controlled and read out by 192 custom Readout Units, which employ commercial SRAM-based FPGAs and will operate in an ionising radiation field, requiring...
FELIX, the PCIe based framework has been used in the DAQ system of ATLAS Phase-I upgrade and the APA (Anode Plane Assemblies) readout in Single-Phase ProtoDUNE experiment. For the ATLAS HL-LHC upgrade, the fiber optical links from front-ends will have higher speed. This manuscript introduces a FELIX demonstrator board with PCIe interface designed for the HL-LHC upgrade. In this board, 25+ Gbps...
The UFSD group of Turin is working at the development of custom front-end electronics for the read-out of thin silicon sensors with moderate internal gain, aiming at high-precision time tagging applications. The development of specific ASIC for timing at INFN-Torino started in 2016. The first two ASIC prototypes, TOFFEE and ABACUS, have been successfully tested in our laboratories and at...
Ten ”slice test” triple-GEM detectors were installed into the CMS endcap in 2017. Data was recorded in 2017-2018, using both cosmic ray muons and LHC collisions. During the slice test, a loss of VFAT2 input channels was observed, with two detectors exhibiting rapidly-increasing channel loss beginning mid-2018.
Concurrent investigations into the cause of the channel loss were launched,...
Single Event Effects represent one of the main challenges for digital designs exposed to ionizing particles in high energy physics detectors. Radiation hardening techniques are based on redundancy, leading to a significant increase in power consumption and area overhead. This contribution will present the SEE hardening techniques adopted in the pixel and strip readout ASICs of the PS-modules...
TCP has been widely used in readout systems. SiTCP is hardware-based TCP stack for Gigabit Ethernet, it realizes direct access and transfer of the data up to 949 Mbps in the memory of FPGA by utilizing TCP communication. The data rate multiplies with the development of pixel detectors for smaller pixels and higher frame-rates. The existing GbE design is no longer satisfied the requirement of...
The Institute of Electronic Systems (ISE) of shall design and deliver hundreds of pieces of various control, signal distribution, and safety modules to be used at the European Spallation Source research facility by the Low-Level RF control, Phase Reference, and Beam Diagnostic systems. This contribution presents the design, as well as strategies and results of acceptance testing of selected...
For identification of neutron-antineutron pair production events in the CMD-3 experiment (BINP, Russia) near threshold is necessary to measure the particles flight time in the LXe-calorimeter with accuracy of about 3ns. The duration of charge collection to the anodes is about 5mks, while the required accuracy of measuring of the signal arrival time is less than 1/1000 of that. Besides, the...
The MAROC chip was dedicated to MaPMT readout, and its third generation was backup solution in the front-end electronics of the RICH-LHCb Upgrade. Given the expected radiation environment for RICH, the MAROC3 was tested with 35 MeV proton beam at the Nuclear Physics Institute in Juelich, Germany. Investigated samples had the behavior recorded using a dedicated test bench. An increasing in...
The Vertex Locator of the LHCb will be upgraded in 2020. As the installation is approaching all the electronics have to be verified and tested. In this poster, the final test setup for all the components and the procedures accomplished will be described. Problems detected and solutions adopted will be explained.
This process goes from visual inspection test of the different boards or bare...
Silicon Photomultipliers (SiPM) are beginning to be actively used in high-energy physics experiments (CMS, LHCb, ATLAS in CERN), therefore careful study of the effect of high radiation fields on the operation of these devices is necessary. This work studies the effect of irradiation with fast neutrons on the work of SiPM (manufacturing: Hamamatsu Photonics K.K.) with an active area of 1 $mm^2$...
The RD53A read-out chip (65 nm CMOS) is a large-scale demonstrator for ATLAS and CMS phase 2 pixel upgrades. It is one of the key elements of the serial powering scheme for the next generation of pixel detectors. The susceptibility of the RD53A chip with respect to external EM noise has an impact on the integration strategies (grounding and shielding schemes) and operating conditions of future...
The Daughterboard (DB) is the readout link and control board that interfaces the front-end and off-detector electronics for the HL-LHC of the the ATLAS Tile Calorimeter. The DB sends high-speed readout of digitized PMT samples, while receiving and distributing configuration, control and LHC timing. A redundant design, Xilinx SEM, TMR, FEC and CRC strategies minimize single failure points while...
The compact structure of the HGTD proposed for the High Luminosity ATLAS detector upgrade at the CERN LHC requires a design to match the tight mechanical and electrical constraints. Our solution with a flexible printed circuit manages the signals to read out and control the modules, to bias the sensors with high voltage and to power the ASIC. It is crucial to match the characteristic impedance...
The Endcap Timing Readout Chip (ETROC), being developed for the CMS Endcap Timing Layer (ETL) for HL-LHC, is presented. Each endcap will be instrumented with a two-disk system of MIP-sensitive LGAD silicon devices to be read out by ETROCs for precision timing measurements. The ETROC is designed to handle a 16×16 pixel cell matrix, each pixel cell being 1.3x1.3 mm^2 to match the LGAD sensor...
This paper presents the design and test results for the line driver (eTx) and the line receiver (eRx) in the lpGBT, fabricated in 65 nm CMOS technology. The two circuits implement the physical layer of the bi-directional eLink interface of the lpGBT. The eTx is a single-ended-to-differential driver with programmable pre-emphasis and driving current. The eRx is a differential-to-single-ended...
The Cavity Simulator reproduces the behavior of superconducting cavities and high power amplifiers used in the medium and high beta sections of European Spallation Source (ESS) linac. The device is foreseen to be used for tests and development of the ESS’s LLRF control system. High-performance Xilinx Kintex Ultrascale FPGA runs dedicated firmware, which performs all calculations including the...
A front-end ASIC for 4D tracking is presented. The circuit includes a charge-sensitive amplifier, a discriminator with programmable threshold, and a time-to-digital converter. A prototype has been designed and integrated in 28 nm CMOS technology. The presented design is part of a project aiming at reaching a high resolution both in space and in time, to provide front-end circuitry suitable for...
The first level (L0) muon trigger of the ATLAS experiment will be upgraded to operate at the High Luminosity LHC.
The selectivity of the current L0 muon trigger is limited by the moderate spatial resolution of RPC and TGC. The MDT chambers currently used for precision tracking will be therefore included to improve the momentum resolution and the redundancy.
A hardware demonstrator of...
The Cooling Storage Ring of the Heavy Ion Research Facility in Lanzhou (HIRFL-CSR) is constructed to study nuclear physics and relative applications. The experiments at the HIRFL-CSR drive the development of new detectors. Aiming to reduce the developing time and cost of each detector system, a Versatile Readout Platform (VRP) has been designed as a tentative common readout platform for the...
Results from the Phase 1 Upgrade of the CMS Level-1 Calorimeter Trigger are presented. The upgrade was completed before the 2016 data-taking and the system served until end of Run II in 2018. The hardware uses Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links and operates in microTCA chassis. Innovations are introduced, such as embedded linux on trigger processing boards and simultaneous...
The High Voltage (HV) system of TileCal, the ATLAS central hadron calorimeter, needs to be upgraded during the so called Phase II Upgrade of the LHC for the HL-LHC. In thw proposed solution, the HV regulation boards are moved away from the detector and deployed in the counting room, safe from radiation damages and with permanent access for maintenance. This option requires a new layout with...
The VMM3a is a System on Chip (SoC) custom Application Specific Integrated Circuit (ASIC). It will be used as the front ASIC for both Micromegas and sTGC detectors of the ATLAS Muon New Small Wheels upgrade at CERN. Due to its highly configurable parameters, it has been proposed a variety of tracking detectors and another experiments. It is fabricated in the 130nm Global Foundries 8RF-DM...
We present here the design and performance of the OBDT board, which is the new prototype built to substitute the CMS DT muon on-detector electronics. The OBDT is responsible of the time digitization of the DT signals, allowing further tracking and triggering of the barrel muons. It is also in charge of the slow control tasks of the DT chamber systems. A prototype of this board has been...
ALTIROC1 is a 25-channel ASIC designed to readout the 5 x 5 matrix of 1.3 mm x 1.3 mm x 50 µm Low Gain Avalanche Diodes (LGAD) of the ATLAS HGTD detector. The targeted combined time resolution of the sensor and the readout electronics is 50 ps/hit. Each ASIC channel integrates a RF preamplifier followed by a high speed discriminator and two TDCs for Time-of-Arrival and Time-Over-Threshold...
The central building blocks of the ATLAS Strip Tracker Upgrade are the staves and petals which host up to 14 modules per side. The incoming data is sent to the EoS and multiplexed by the lpGBT chips on 10 Gbit/s links and sent via optical transmitters (VL+) off-detector. The EoS is a critical component for the upgrade, sitting at a single-point-of failure location. Prototype boards have been...
The CMS Detector will be upgraded for the HL-LHC to include a MIP Timing Detector (MTD). The MTD will consist of barrel and endcap timing layers, BTL and ETL, respectively, providing precision timing of charged particles. The BTL sensors are based on LYSO:Ce scintillation crystals coupled to SiPMs with TOFHIR ASICs for the front-end readout system. A resolution of 30 ps for MIP signals at a...
For the third running period of the CERN LHC, the ALICE experiment will
undertake several upgrades of its sub-detectors. One of the detectors to be
upgraded is the Inner Tracking System, featuring the new ALPIDE pixel chip.
Control and readout of the 24120 chips are handled by 192 custom FPGA-
based readout units. Each readout unit can forward 9.6Gbps of data to another
custom PCIe card that...
Today communication protocols (32Gbps PCIE Gen5, 112Gbs PAM4, ...) and FPGAs transceivers speeds are pushing
designer to hardware designs constraints, PCB material choice and layout constraints that where almost never considered years ago.
This presentation is an extract of a CCES technical training, and its purpose is to cover some of the theorical aspects of "high speed",
as well as some...
The first running implementation on FPGA of a histogram-based trigger primitive generator for the CMS Drift Tubes at the HL-LHC is presented. This project is driven by the need to generate a trigger by processing the charge collection times, acquired by means of a TDC, and asynchronously shipped to the back-end. We review the design of the bunch crossing evaluation, its implementation on FPGAs...
High Density Interconnect hybrids are being developed for the CMS Tracker Phase Two Upgrade for the HL-LHC. These hybrids are flexible circuits with flip-chips, passives and connectors laminated to carbon fibre composite stiffeners. The wirebonding of sensors and the soldering requirements for these components requires an almost perfectly flat surface. A lamination process is proposed, focused...
The Electron Feature Extractor (eFEX) is one of the core subsystems for the Phase-I upgrade of the ATLAS Level-1 Calorimeter Trigger. In Run 3, the eFEX will identify isolated e/g and tau candidates with much higher discriminatory power than in Run 2. The eFEX subsystem consists of 24 eFEX modules housed in two ATCA shelves. Each eFEX module has up to 200 optical input/output links and more...
The upgraded CMS tracker at the HL-LHC will feature new silicon modules with a macro-pixel sensor and a strip sensor on top of each other. The modules require three supply voltages (1.0V, 1.2V, 2.5V), which are provided in a two-stage DC-DC conversion powering scheme. Two DC-DC buck converters are supplied in parallel from the first powering stage. A four-layer flexible power hybrid based on...
Here we describe the DECAL Monolithic Active Pixel Sensor (MAPS) for digital electromagnetic calorimetry. The sensor consists of a matrix of 64x64 55um pixels, and provides a readout at 40MHz of the number of particles which have struck the matrix in the preceding 25ns. It can be configured to report this as a total sum across the sensor (equivalent to the pad of an analogue calorimeter) or...
In view of the High-Luminosity LHC, the Compact Muon Solenoid (CMS) experiment is planning to replace entirely its trigger and data acquisition system. Novel design choices are being explored such as ATCA prototyping platforms and newly available interconnect technologies proving links up to 28 Gb/s. Higher-level trigger object reconstruction is performed through large scale FPGAs (such as...
The CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a $180$nm HR-CMOS Imaging Process. The chip, designed in the context of the CLIC tracking detector study, comprises a matrix of ${16\times128}$ detector channels, each measuring ${300\times30}\mu$$m^{2}$. To ensure prompt charge collection, each channel is segmented in eight collection diodes, each containing...
The luminosity increase of the LHC in Phase-II calls for an in-depth redesign of the entire MDT readout chain. While the high rate of primary detector signals requires increased bandwidth at each level of the data path, the MDT readout must, in addition, supply accurate coordinate information to the trigger system, leading to more reliable identification of high-pT tracks. The pre-selection of...
The LF2 is a depleted MAPS prototype chip produced in the LFoundry 150 nm HV-CMOS process on 500 Ωcm and 1900 Ωcm wafers. The chip includes two monolithic matrices. One matrix of 40 rows x 78 columns contains 50 x 50 μm2 pixels each with a charge sensitive amplifier, a shaper, and a discriminator, which are readout by a digital block with FE-I3 column drain architecture. A 26 x 52 photon...
The Belle II Experiment relies on an online level 1 trigger system to reduce the background and achieve the targeted frequency of 30 kHz. Here the basis for all trigger decisions based on data from the Central Drift Camber is the track segment finding. To improve both efficiency and maintainability we restructured the original combinatorial approach to finite state machines. The new...
Sub 65-nm technologies can offer to engineers huge advantages for the design of high-density and low power circuits and for the integration of high complexity System-on-Chips. Transistors and gates are almost free for the creative designer, but yet their correct integration requires an exponentially increasing investment in tools and training, and a totally new approach to verification, all...
The design and measurement results of different versions of ultra-low power fast 10-bit SAR ADC prototypes, fabricated in CMOS 65 nm technology, are presented. The prototypes use different capacitive DACs, different DAC switching schemes and different asynchronous logic. All prototypes are fully functional, achieving good linearity (with both INL and DNL below 1 LSB) and ENOB around 9.3 for...
The readout electronics of the CMS electromagnetic calorimeter (ECAL) barrel will be upgraded to meet the Level-1 trigger requirements at HL-LHC. The new very front-end (VFE) electronics will mitigate the increasing noise from the avalanche photodiodes (APDs), discriminate against anomalous APD signals, and provide the extra bandwidth needed to maintain the integrity of the detector signal...
The CMS detector will undergo a major upgrade for Phase-2 of the LHC program: the HiLumi LHC, starting around 2026. The Phase-2 CMS back-end electronics will be based on the ATCA standard, with node boards receiving the detector data from the front-ends for processing via custom, radiation-tolerant, optical links. An ATCA hub board, the DAQ and Timing Hub (DTH), will provide the interface...
SALT is a 128-channel readout ASIC, designed in CMOS 130~nm process, for silicon strip detectors in the upgraded Tracker of LHCb experiment. It extracts and digitises analogue signals from the sensor, performs digital signal processing and transmits serially the output data. SALT uses the innovative architecture comprising of a low power analogue front-end and a 40~MSps 6-bit ADC in each...
The architecture and experimental results for the downlink Equalizer (Eq) and Eye Opening Monitor (EOM) circuits in the lpGBT ASIC are presented. The 2.56 Gbps downlink NRZ data is received by a line receiver that is followed by a Continuous Time Linear Equalizer (CTLE) with programmable transfer function. The EOM circuit scans the output of the Eq with a time resolution of 6.1 ps and a...
The High Luminosity upgrade of the LHC (HL-LHC) is foreseen to increase the instantaneous luminosity by a factor of five over the present LHC nominal value. The resulting, unprecedented requirements for background monitoring and luminosity measurement create the need for new high-precision instrumentation at CMS, using radiation hard detector technologies. This contribution presents a system...
RD53A is the first prototype of RD53, the pixel detector front-end chip that will be used by the ATLAS and CMS experiments at CERN during HL-LHC, starting operation in 2026. It is implemented using 65 nm technology and it transmits data using up to four lanes running at 1.28 Gbps each. This presentation will describe the implementation of a first readout chain of the RD53A using the ATLAS...
A 32 channel, 15ps resolution, Kintex 7 FPGA-based TDC DAQ for time-of-flight and time-over-threshold measurement is demonstrated along with a comparison to previous works. Results include 11ps mean bin size, less than 4ps differential nonlinearity, and less than 10ps of integral nonlinearity. Linearity is improved by multichain averaging with comparison of 1, 2, and 4 chains pre and...
To update associated electronics with fast-timing resistive plate chamber (RPC) detectors, we present here a multi-channel time-tagging module implemented on a low-end and low-power cyclone V FPGA. A key part in each channel has a time-to-digital converter (TDC) in tapped-delay-line (TDL) architecture (built with delay line and associated registers, fine-time encoder, coarse-time counter and...
The Inner Tracker silicon strip detector (ITk Strips) a part of the ATLAS upgrade for the HL-LHC. It employs a parallel powering scheme for the bias high voltage and the low voltage power. To reduce the amount of services, on-module DCDC conversion and high voltage switching is required. These features are implemented on the Powerboard using a step-down buck converter (bPOL12V) to drop the low...
As for the High Luminosity LHC the instantaneous luminosity will be increased by a factor 3, an efficient trigger selection will be crucial. To reduce signal latency, the proximity of the readout electronics to the detector becomes very important. A custom designed 63U rack has been chosen as a house for the ATCA based systems allowing installing 50% more shelves in the detector proximity. The...
The LHC Phase II Upgrade of the ATLAS Tile Calorimeter (TileCal) implies a new readout and trigger architecture. The on-detector readout electronics will transmit detector data to 32 Tile PreProcessor (TilePPr) boards in the counting rooms at the LHC frequency, sending selected data to the ATLAS FELIX and interface with the trigger systems. Each TilePPr is composed of four Compact Processing...
Serial powering is the baseline option for the pixel detectors in both the ATLAS and the CMS experiment targeting the phase II HL-LHC upgrade. The Shunt-LDO regulator is integrated in the front-end chips to generate the required supply voltages. A new compensation scheme has been developed to operate stable with large Low-ESR load capacitances. A two-stage bandgap voltage reference circuit has...
For the next upgrade, the ALICE experiment will use a Common Readout Unit (CRU) at the heart of the data acquisition system. The CRU, based on the PCIe40 hardware designed for LHCb, is a common interface between front-ends, computing system and the trigger and timing system. The 475 CRUs will interface 10 different sub-detectors with 3 sub-systems and reduce the total data throughput from 3.5...
The failure of a first DCDC converter in the power distribution network of the CMS pixel detector system on October 5th, 2017, might have been due to a single failure and did not raise particular concern. However, it was soon followed by a steady rate of failures of DCDCs in random positions in the detector. Projections of this rate to the future led to an ominous scenario where, without...
Highly segmented digital tracking calorimeters (DTC) consist of multiple layers of high-granularity pixel detector CMOS sensors and absorption/conversion layers. Two separate prototypes are being developed: (1) an electromagnetic calorimeter (FoCal) for a proposed ALICE upgrade (during LS3) and (2) a hadronic calorimeter for medical proton CT imaging (pCT). These prototypes employ the ALPIDE...
The LHC machine will be upgraded to increase its peak luminosity and possibly reach an integrated luminosity of $3000-4500\;$fb$^{-1}$. The CMS experiment is called for an upgrade to keep up with the new challenges such as unprecedented radiation environment, requiring high resilience, and increased number of events per bunch crossing, requiring higher detector granularity. Consequently, both...
We present a 32-channel data acquisition system using the PSEC4A chip and initial applications as a readout system for neutron detectors at Sandia’s Z Pulsed-Power Facility. The PSEC4A is an 8-channel, 10 GSa/s waveform recording ASIC with an analog bandwidth of 1.9 GHz, which also incorporates multi-event buffering to reduce latency induced by close-in-time triggers. In the 32-channel...
High Voltage-CMOS (HV-CMOS) sensors are the sensor technology of choice for the pixel tracker in the Mu3e experiment at PSI in Switzerland. In this contribution, timing resolution down to 0.5 ns is obtained. Simultaneously, power consumption is held below 28 μW in a pixel size of 60 μm2, enabling 4D tracking in a high-density array. Timing errors due to signal amplitude variations considered...
The ATLAS experiment will get a new inner tracker (ITk) during the phase II upgrade. The innermost part will be a pixel detector. A new Detector Control System (DCS) is being developed to provide control and monitoring of the ITk pixel detector. The DCS Controller is a CANopen based Application Specific Integrated Circuit foreseen to independently monitor a serial power chain. The final chip...
A high-density electrode array is being developed for Neutrinoless Double-Beta Decay search in high-pressure gaseous TPC. A sensor, Topmetal-S, is designed to have mm-sized electrode, followed by an amplifier and an ADC based on a 0.35um CMOS process. The Topmetal-S array can collect charge directly without gas avalanche gain to achieve high energy and spatial resolution simultaneously. To...
A mixed-signal ASIC developed to readout silicon photomultipliers (SiPM) at low temperature is presented. The chip is designed in a 110 nm CMOS technology. Both single photon counting and Time-over-Threshold (ToT) operating modes are supported. In single photon counting mode an event rate of up to 5 MHz per channel can be accommodated. The time resolution is 50 ps and the target power...
In the 2018 summer the PolarQuEEEst experiment accomplished a measurement
of cosmic rays flux in the Arctic. The detector, installed on a sailboat, was based on
scintillation tiles read by a total of 16 SiPM.
A multi-channel board (called TRB) has been designed to process the discriminated SiPM signals providing self-trigger capability and
time-to-digital conversion. It was based on a...
Results of analyzes of Time-of-Arrival measurements with Low-Gain-Avalanche-Diode sensors were carried out for the amplitude or time-over-threshold corrected leading edge measurements and for practical realization of Constant-Fraction-Discrimination based on ideal delay and RC-type low-pass filtering delay. The Expected current waveforms, resulting from modeling of a sensor and application of...
The design of the Level-0 endcap muon trigger system for the ATLAS experiment at HL-LHC and the status of the development are presented. The new system reconstructs muon candidates with an improved momentum resolution by combining signals from various subdetectors. The trigger efficiency is estimated with Monte-Carlo simulation to be >90%. The trigger rate is also estimated with proton-proton...
ATLASPIX3 is a 2cm x 2cm HVCMOS sensor designed to meet the specifications of layer 4, ATLAS inner tracker. ATLASPIX3 is a depleted monolithic CMOS pixel detector. The chip size allows the construction of quad modules of equal size as that of hybrid sensors. ATLASPIX3 supports triggered readout. The hit information is transmitted via 1.28 Gbit/s. The clock, trigger and configuration bits are...
LHCb detector is a general purpose experiment instrumented in the forward region
at the LHC, specialized in b- and c- physics, new physics and CP violation. The Vertex
Locator (VELO) detector is being upgraded along with the rest of the tracking system
and readout architecture during 2019-2020. The aim of this poster is to present the
architecture of the control and readout firmware on the...
SUPIX-1 is the first version of high spatial resolution monolithic active pixel detector prototype led by Shandong University Pixel Group which serves for CEPC tracker system. The chip has 18μm epi-layer with the resistance of 1kΩ·cm using TowerJazz 0.18 μm technology. Each chip has 9 sub-matrices, 64 rows by 16 columns for each matrix, which gives 16 parallel analog outputs with rolling...
Coming developments in X-ray photon sources will increase signal rate and intensity. Similar performance improvements are needed in a new multi-mega pixel imager. Its readout ASIC is to be based on charge-integration, be compatible with different sensor types, include adaptive-gain (to achieve single-photon resolution and high dynamic range), radiation-hard solutions and circuits for rapid...
We will present the design and the performance of two drivers in 65 nm TSMC technology, for Silicon Photonics Mach-Zehnder Modulator (MZM) devices, able to withstand radiation levels of up few 1016 n/cm2 and ~0.5 - 1 Grad. The drivers use a CML architecture and are optimized for >500 Mrad and a target a bit rate between 5 to 10 Gbps. They have been tested up to 800 Mrad showing about 25%...
This work is concerned with the design and the characterization of digital-to-analog current converters, developed in a 65 nm CMOS technology, conceived for threshold tuning of front-end channels at the HL-LHC experiment upgrades.
Two DAC structures were integrated in a small prototype chip, that was submitted in August 2018 in the framework of the RD53 developments. The prototype has been...
This paper presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 4 ps, fabricated in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. To achieve the low resolution, the delay elements are implemented using a new interlocked interpolation technique to reduce the Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) error....
Xilinx Zynq SoCs are used by the CMS TDAQ in its back-end electronics since LHC Run-2, between 2015-2018. For the Phase 2 upgrade of the LHC, about 1000 devices will be deployed, comparable to the number of High Level Trigger (HLT) nodes today. This scale presents challenges for the SoC integration in the experiment network, system administration, network management, booting process and root...
During the current major LHC shutdown (2019-2021), the ATLAS experiment at CERN is moving to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX functions as a router between custom serial links and a commodity switch network, which uses industry-standard technologies to communicate with data...
In this work, we present a customized pn depletion type Mach-Zehnder modulator (MZM) as well as a fully integrated wavelength division multiplexing (WDM) transmitter design with the merits of high bandwidth and radiation hardness, aiming to upgrade the optical data transmission of future detector systems. A detailed characterization of the modulators on modulation efficiency and RF response...
The Concentrator Integrated Circuit ASIC is a front-end chip for both Pixel-Strip and Strip-Strip modules of the future Phase-2 CMS Outer Tracker upgrade. It collects the digital data coming from eight upstream front-end chips, formats the signal in data packets containing the trigger information from eight bunch crossings and the raw data from events passing the first trigger level, and...
The upcoming upgrade of the readout system of the ATLAS experiment at the LHC at CERN is based on the Front-End LInk eXchange (FELIX) system. As part of this upgrade, approximately 120 custom PCIe cards are being produced by an industrial partner, based on a hardware design developed within the collaboration. Such a large production requires detailed Quality Assurance/Quality Control...
For the Long Shutdown 2 upgrade of the ALICE experiment, a new Inner Tracking System (ITS) is under development, based on the ALPIDE Monolitihic Active Pixel Sensor (MAPS) chip.
Data readout from the ALPIDE chips is performed by 192 Readout Units (RU), which are also responsible for trigger distribution, monitoring, configuration, and control of the sensor chips. Monitoring and control of...
KARATE (KArlsruher high RAte TEst) is a new system to stress the readout chain of strip modules for the future CMS Outer Tracker at HL LHC. The readout chain of a module starts with CMS Binary Chips (CBC) connected simultaneously to two sensors. The sparsified output is send out via an optical link. KARATE injects patterns with varying pulse heights, occupancies and trigger rates into the CBC...
Multimode interferometers (MMI) are key components for high-bandwidth transceivers in upgrading the data transmission of future detector systems. We present 2 conventional high-performance MMIs fabricated on a 250nm SOI platform with different splitting ratios which operate as 50:50 power splitter for Mach-Zehnder modulators and as 86:14 power splitter for loop control in future transceiver...
In this article we describe the measurement results on an “AARDVARC” prototype in 130 nm. AARDVARC is a multi-channel waveform digitizing and processing Application Specific Integrated Circuit (ASIC) front-end. We report on various performance metrics: fast sampling (10-14 Gsa/s), deep storage (32K samples), timing resolution (better than 5ps), low power consumption (<100mW/channel).
Reliable measurement of clock signal parameters is important in precise-timing applications. Such parameters include frequency, phase, duty cycle and channel-to-channel skew. Especially in applications in which test time for multiple channels is a significant factor, efficient parallelization of measurements is crucial, while often coming with significant extra cost. This work presents an...
The KINTEX-7 FPGA is to be used in the new digital readout of the upgraded LHCb-RICH sub-detectors. This summary presents the measurements done to evaluate the reliability of this FPGA under ionizing radiation exposure with different types of particle beams: ions, protons and X-rays. Single-event effect cross-sections for critical resources - such as Flip-Flops, RAM blocks, configuration...
Triple-GEM has been adopted for the GE2/1 upgrade of the forward muon detector at CMS for the High Luminosity LHC. GE2/1 chambers are segmented in 4 modules. Each module is equipped with the Optohybrid (OH) interfaced to 12 VFAT3 ASICs. The OH uses GBTs for the readout path and is equipped with a Xilinx Artix-7 FPGA for the trigger data processing.
In this presentation we report on our...
Modern VLSI technology allows the development of new class X-ray imaging detectors capable of capturing an image in various energy ranges in one shot. Such spectroscopic imaging detectors have a high demand for the spatial and energy resolution of individual photons. With decreasing size of pixels, the charge cloud generated by the primary photon interaction, and in high-Z materials also by...
At INFN-Torino, ASICs for readout applications of detectors were designed in several technologies, and are now under development. The 110 nm CMOS UMC technology is applied too. This technology has been chosen for its lower cost with respect to IBM or TSMC, even if there was not a systematic characterization for what concerns the radiation tolerance. Obviously, it is important to know the...
The COMET detector will include a electromagnetic calorimeter (ECal). The ECal signals will used for energy deposition measurement and for triggering. For triggering, the calorimeters signals will transformed into special short-shaped analog signals. These signals will then digitally processed with special algorithm, which allows one to obtain a set of logic signals necessary for event...
The Compressed Baryonic Matter experiment (CBM) will study rare probes in a heavy-ion environment at high interaction rates of up to 10 MHz. The observation of detached vertices requires a topological trigger, which is realized in software. CBM opted for a free-running readout, for reasons similar to LHC-b. The primary beam is delivered by a slow extraction synchrotron. To be able to operate...
We present tests with a scanning micro-focus photon beam of the miniMALTA DMAPS prototype developed for ATLAS ITk. Tests were carried out at Diamond Light Source which provided a 2um beamspot to be scanned in 1um steps. This allows the in pixel efficiency to be measured directly with high statistics. Three pixel design variations were measured, the standard design, a deeper p well design and...
This paper presents the design, architecture and experimental results of the ljCDR (Low Jitter CDR) in the lpGBT (Low Power Gigabit Transceiver). The chip includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. The CDR employs a novel loop architecture with a high-speed feed forward loop...
The Low Power GigaBit Transimpedance Amplifier (lpGBTIA) is the optical receiver amplifier in the lpGBT chipset. It is a highly sensitive transimpedance amplifier designed to operate at 2.56 Gbps. It is implemented in a commercial 65 nm CMOS process.
The device has been designed for radiation tolerance and, in particular, to accommodate the radiation effects in photodiodes that manifest...
In this paper, an lpGBT sub-system for environmental monitoring and control of experiments is presented. The monitoring part contains an 8 external and 8 internals inputs followed by a 16-to-1 multiplexer, instrumentation amplifier with selectable gain and a 10-bit ADC. A constant current source can be enabled on each external input to facilitate resistances measurements. Internal channels are...
CMS is planning to install GEM chambers as part of the Muon upgrade for High Luminosity Operation at the LHC. The front-end ASIC (VFAT3) has been produced in volume together with its hybrid PCB. This paper describes the design of a custom test bench for the production Quality Control (QC) of the VFAT3 hybrids. The full QC procedure incorporates calibration and performance measurements,...
September 2019 marks 20 years since the signature of the Medipix2 Collaboration agreement. Since then 3 generations of pixel detector readout chips have been or are being developed: Medipix2 and Timepix (with recently the addition of Timepix2), Medipix3 and Timepix3 and finally Medipix4 and Timepix4. The Medipix chips have sought to provide high-rate spectroscopic photon counting with...
The new LHCb Vertex Locator for LHCb, comprising a new pixel detector and readout electronics will be installed in 2020 for data-taking in Run 3 at the LHC. The electronics centre around the "VeloPix" ASIC at the front-end operating in a triggerless readout at 40$\,$MHz. Custom serialisers send zero-suppressed data from the VeloPix at a line rate of 5.13$\,$Gb/s. Signal integrity tests of...
