Speaker
Description
The CMS detector will undergo a major upgrade for Phase-2 of the LHC program: the HiLumi LHC, starting around 2026. The Phase-2 CMS back-end electronics will be based on the ATCA standard, with node boards receiving the detector data from the front-ends for processing via custom, radiation-tolerant, optical links. An ATCA hub board, the DAQ and Timing Hub (DTH), will provide the interface between the back-end nodes and the central Trigger, Timing, and DAQ systems. This paper presents the first measurements performed on the initial prototype production, with a focus on clock quality and serial link performance.
Summary
The upgraded CMS detector will be read out at an unprecedented data rate of up to 50 Tb/s with an event rate of 750 kHz, selected by the level-1 hardware trigger, and an average event size of 7.5 MB. The back-end electronics will be based on the ATCA standard, with node boards receiving the detector data via optical links from the front-end electronics and processing them.
The CMS DAQ and Timing Hub will connect to all back-end node boards. The DTH is responsible for the distribution of clock, trigger, and fast-control data from the central trigger control system to all back-end electronics and the handling of throttling signals in the other direction. The DAQ interface for the event data uses point-to-point optical links connected to back-end node boards and runs a custom lossless protocol (“SlinkRocket”). The event data are aggregated in the DTH and transmitted via standard commercial network (with links of 100 Gb/s or higher) and protocol (such as TCP/IP) to event building computer nodes at the surface.
The introduction of timing detectors for Phase-2 CMS, aiming for a 30 ps precision on individual detector hits, strongly tightens the requirements on the clock and timing information distributed throughout the experiment, with different sub-detectors introducing different requirements.
At TWEPP 2018 we presented the design of the first DTH prototype, and discussed some of the design challenges encountered. Other contributions summarised the phase noise studies performed as part of the component selection for the DTH. The DTH P1 board features an FPGA (KU15P) with ancillary components for clock recovery and jitter-cleaning, and serial links to the back-plane implementing the clock, timing, trigger and throttling functions. A second FPGA (KU15P) with mid-board optics (FireFly) connecting to the back-end boards, and QFSP+ cages connecting to the standard commercial network, implements the DAQ event flow functions.
The current paper presents first measurements performed on the initial prototype production, with a focus on clock quality and serial link performance via back plane and mid-board optics. First results will be presented with a proof-of-principle setup of a DTH and a prototype back-end board on the timing performance.
We will conclude with a brief look back at the design and production experience of the first DTH prototype boards, and a look forward to the next evaluation steps and future prototype boards and systems.
