SUPIX-1 is the first version of high spatial resolution monolithic active pixel detector prototype led by Shandong University Pixel Group which serves for CEPC tracker system. The chip has 18μm epi-layer with the resistance of 1kΩ·cm using TowerJazz 0.18 μm technology. Each chip has 9 sub-matrices, 64 rows by 16 columns for each matrix, which gives 16 parallel analog outputs with rolling shutter readout mode, and the chip sensitive area is 2mm*7.88mm. The readout system is based on XILINX KC-705 FPGA board with PCI-e data transmission mode.And the pixel sensor gain was calibrated with Fe-55 K-α peak.
SUPIX-1 which taped out in 2016, is the first monolithic active pixel sensor prototype in Shandong University with TowerJazz 0.18 μm technology. This prototype serves for the Circular Electron Positron Collider (CEPC) tracker system. In order to calibrate the sensor gain of SUPIX-1, The data acquisition system was set up at Shandong University. The system consists: Device under test (DUT) board, which carries the chip under test. Main board, which convert the analog output from the chip under test to digital signal and the effective bits is 14. FPGA board, which encode the output from the main board and transmit the data to the PC disk through PCI-e protocol, the FPGA board used for the test system is XILINX KC-705. The sensor gain calibration was carried out with Fe-55 K-α and K-β peak. The analysis system for the data acquired is based on ROOT.