Sep 2 – 6, 2019
Europe/Zurich timezone

A 60μm2 HV-CMOS pixel with 0.5 ns timing resolution and 28 μW power consumption for high-density arrays

Sep 5, 2019, 4:55 PM
Poster ASIC Posters


Sergio Moreno (University of Barcelona)


High Voltage-CMOS (HV-CMOS) sensors are the sensor technology of choice for the pixel tracker in the Mu3e experiment at PSI in Switzerland. In this contribution, timing resolution down to 0.5 ns is obtained. Simultaneously, power consumption is held below 28 μW in a pixel size of 60 μm2, enabling 4D tracking in a high-density array. Timing errors due to signal amplitude variations considered special attention to improve time resolution.


HV-CMOS technology was developed some years ago. Large arrays of these pixels are being developed as a prove that this technology can be used in several High-Energy Physics experiments [1]. In this step, it is important to reduce both, the timing uncertainty in detecting particle arrival, and power consumption. In this paper, a HV-CMOS pixel was designed in the 150 nm process of LFoundry to increase timing accuracy. It was integrated in only 60 μm2, consuming just 28μW. Hence, 4D tracking is habilitated with this pixelated technology.
The analog readout integrated in-pixel consists of a sensor bias circuit, a Charge Sensitive Amplifier (CSA), a single folded cascode amplifier, a source-follower and a comparator with a 4-bit DAC for offset compensation. To reduce the time walk, the pixel includes an analog buffer, a delay chain and 5 analog memories needed to sample the rising edge of the pre-amplified signal. The analog sampling permits to perform a linear fit over the sampled voltages and to find the time-of-arrival of the particle. These data allow to correct the time walk off-line and to extract the energy information of the detected particle.
The time of the arrival of the particle is digitally added with a time-stamp (TS) running at frequencies from 40 MHz to 200 MHz. To increase timing resolution, a programmable Time-to-digital converter (TDC) common to the whole pixel array is included in the chip. The coarse phase of the TDC is the Least Significant Bit (LSB) of the TS. The fine phases of the TDC are generated through delays implemented by a chain of buffers. The fine TDC generates 5 phases equally delayed from the TS clock with configurable delays from 0.5 ns to 2 ns. Moreover, each phase has the same rise and fall time. The hit time is defined by the values of the TS and the 5 fine phases. Timing corrections of the hit time of the particle are performed off-line as well.
Compared to similar pixel area detectors, simulations show that the time walk is reduced down to 4.1 ns with a power consumption of 28 μW per pixel, and a maximum timing resolution of 0.5 ns. An ASIC including the presented pixel was sent to fabrication.
[1] I. Perić et al., “Overview of HVCMOS pixel sensors,” J. Instrum., vol. 10, no. 5, 2015.

Primary author

Sergio Moreno (University of Barcelona)

Presentation materials