Intel solutions and tools for ML/DL implementations

513/1-024 (CERN)



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This full day workshop will provide a comprehensive picture of Intel strategy for ML/DL solutions and will give the possibility to understand which are the tools already available today on Intel Architecture, and what will be available soon, to address neural network implementation (Optimized DL frameworks, OpenVino, nGraph). During the workshop Intel is planning to explain and demonstrate the benefit of new instruction set (VNNI – DL Boost) included in the future XEON® Scalable Processors – Cascade Lake. Intel will also provide evidence of the open source project in which has been involved to simplify and how containers can help scaling and provide easy deployment ML/DL projects (Nauta). Looking forward Intel is planning to share more details on future specific products (NNP) targeting Training and Inference acceleration.

Andrea Luiselli ITS Industry Technology Specialist

Andrea Luiselli started working at Intel in 2005. During his 13+ years covered many different role. He started as Channel Application Engineer and Server Platform specialist being responsible for Italian and Swiss market. He also covered sales role being Account Manager for server focused accounts in both Italy and Switzerland and was then successfully supporting Supermicro business as Business Development Manager in EMEA. Starting 2015 Andrea moved to technical enterprise position working with HPC and Enterprise accounts in Italy, Switzerland and Spain growing his experience in HPC/AI market and enabling customers to leverage on Intel latest technology for modern Datacentres needs. Since 2012 Andrea is Technical Spokesperson for Intel in Italy.


Walter Riviera - EMEA AI Technical Solutions Specialist Lead - Intel

Walter joined Intel in 2017 as an AI TSS (Technical Solution Specialist) covering EMEA and he’s now playing an active role on most of the AI project engagements within the Data Centers business in Europe. He is responsible for increasing business awareness regarding the Intel AI Offer, enabling and provide technical support to end user customers, ISVs, OEMs, Partners in implementing HPC and/or Clouds solutions for AI based on Intel’s products and technologies.Before joining Intel Walter has collected research experiences working on adopting ML techniques to enhance images retrieval algorithms for robotic applications, conducting sensitive data analysis in a start-up environment and developing software for Text To Speech applications.


Francisco Perez – FPGA Specialist Applications Engineer

Francisco joined Intel in 2017 as FPGA Specialist Applications Engineer providing technical support to customers in Western Europe. He has 15+ year experience as FPGA design engineer, helping customers in the selection of the most suitable architecture for their projects and solving technical issues in development phases. Now actively engaged in driving adoption of FPGA as hardware accelerators in applications like High Performance Computing, video processing and analytics as well as optimizing Deep Learning inference.

Registration to the Intel workshop
  • Abdeslem Djaoui
  • Ahmad Siar Hesam
  • Alberto Pace
  • Andrea Valassi
  • Dan Guest
  • Dario d'Andrea
  • Dejan Golubovic
  • Guilherme Amadio
  • Gul Rukh Khattak
  • Jean-Roch Vlimant
  • Jennifer Ngadiuba
  • Karolos Potamianos
  • Konstantinos Iliakis
  • Krzysztof Szczurek
  • Lorenzo Moneta
  • Luca Canali
  • Manuel Gonzalez Berges
  • matteo migliorini
  • Nick Ziogas
  • Riccardo Poggi
  • Roland Sipos
  • Ryu Sawada
  • Sioni Paris Summers
  • Sitong An
  • Sofia Vallecorsa
  • Stefan Roiser
  • Vladimir Loncar
  • Yiming Abulaiti
    • 9:00 AM 9:15 AM
      Welcome 15m
      Speakers: Luca Atzori (CERN), Maria Girone (CERN), Guillermo Izquierdo Moreno (Universidad de Oviedo (ES)), Mr Claudio Bellini (Intel)
    • 9:15 AM 9:45 AM
      Intel Strategy for AI and roadmap update (HW & SW) 30m
      Speaker: Andrea Luiselli (Intel)
    • 9:45 AM 10:45 AM
      TensorFlow Scalability 1h
      Speaker: Walter Riviera (Intel)
    • 10:45 AM 11:00 AM
      Coffee break 15m
    • 11:00 AM 11:30 AM
      Performance optimisation of 3DGAN training and inference on Intel architectures 30m
      Speaker: Dr Sofia Vallecorsa (CERN)
    • 11:30 AM 12:05 PM
      Nauta: A multi-user distributed computing environment for DL 35m
      Speaker: Andrea Luiselli (Intel)
    • 12:05 PM 1:40 PM
      Lunch break 1h 35m
    • 1:40 PM 2:40 PM
      OpenVino Development Suite - Demo 1h
      Speaker: Francisco Perez (Intel)
    • 2:40 PM 3:20 PM
      FPGA Solutions for AI 40m
      Speaker: Francisco Perez (Intel)
    • 3:20 PM 3:35 PM
      Coffee break 15m
    • 3:35 PM 4:05 PM
      VNNI DL Boost Demo (CLX remote connection) 30m
      Speaker: Walter Riviera (Intel)
    • 4:05 PM 4:35 PM
      Intel nGRAF 30m
      Speaker: Walter Riviera (Intel)
    • 4:35 PM 4:45 PM
      Q&A / Wrap-up 10m
      Speakers: Luca Atzori (CERN), Maria Girone (CERN), Guillermo Izquierdo Moreno (Universidad de Oviedo (ES)), Mr Claudio Bellini (Intel)