Speaker
Description
We present an integrated analog Front-End (FE) designed in a 65 nm CMOS process optimized for the readout of 6 cm2 Silicon Photomultiplier (SiPM) tiles. It implements a super-common gate preamplifier followed by a newly introduced 4th order fully-differential complex conjugate pole shaper. The circuit can be programmed for various series-parallel SiPM arrangements and peaking times. It consumes 3 mA at 1.2 V supply, with 2 mA in the input transistor. Circuit simulations yield amplitude measurement resolution of <0.03 single photo-electrons rms and single-photon-timing-resolution of <30 ns rms for a SiPM capacitance of 3.4 nF/cm2 and an input range of 100 photo-electrons. The FE is designed to be operational in cryogenic environments down to a temperature of 77K and, therefore, is a viable candidate for the photon-detector readout in the nEXO experiment. Fabrication of a 16 channel ASIC comprising this FE block is planned in the second half of 2020.
