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    PRR of the NSW Trigger Processor Part 2

    6 May 2020
    CERN
    Europe/Zurich timezone

    Contribution List

    10 out of 10 displayed
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    1. 1. Review procedure
      Hucheng Chen (Brookhaven National Laboratory (US))
      06/05/2020, 14:00
    2. 2. Introduction & Review Scope
      Stephanie Ulrike Zimmermann (Albert Ludwigs Universitaet Freiburg (DE))
      06/05/2020, 14:10
    3. 8. Micromegas: L1A and readout (thru carrier). Algorithms and time alignment.
      Nathan Felt (Harvard University (US)), Nathan Felt (Unknown), Thiago Costa De Paiva (University of Massachusetts (US))
      06/05/2020, 14:25
    4. 11. sTGC stage-0: L1A and readout (thru carrier). Stage-0 algorithm; time alignment
      Enrique Kajomovitz Must (Department of Physics), Enrique Kajomovitz Must (Technion, Israel Institute of Technology)
      06/05/2020, 14:55
    5. 12. Merge block, and output formatter to SL.
      George Chatzianastasiou (University of Innsbruck (AT))
      06/05/2020, 15:25
    6. 7. Results of combined tests with SL. Fixed latency. Latency measurements.
      Lorne Levinson (Weizmann Institute of Science (IL))
      06/05/2020, 15:55
    7. 3. Carrier v3 design.Validation/test results (Bucarest/Samway, standalone)
      Andrei Scurtu (Samway SRL), Sorin Martoiu (Horia Hulubei National Institute of Physics and Nuclear Enginee)
      06/05/2020, 16:35
    8. 4. Board test protocol and procedures (for series production); acceptance criteria
      Ricardo Di Curzio Lera (University of Massachusetts (US)), Thiago Costa De Paiva (University of Massachusetts (US))
      06/05/2020, 17:00
    9. 5. Production plan and schedule
      Mihai Savu (Samway Electronic), Sorin Martoiu (Horia Hulubei National Institute of Physics and Nuclear Enginee)
      06/05/2020, 17:30
    10. 6. Installation plans @ P1 and commissioning
      Alexander Naip Tuna (Harvard University (US))
      06/05/2020, 18:05

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