PRR of the NSW Trigger Processor Part 2

Contribution List

1. Review procedure

Hucheng Chen (Brookhaven National Laboratory (US))

5/6/20, 2:00 PM

2. Introduction & Review Scope

Stephanie Ulrike Zimmermann (Albert Ludwigs Universitaet Freiburg (DE))

5/6/20, 2:10 PM

8. Micromegas: L1A and readout (thru carrier). Algorithms and time alignment.

Nathan Felt (Harvard University (US)), Nathan Felt (Unknown), Thiago Costa De Paiva (University of Massachusetts (US))

5/6/20, 2:25 PM

Trigger Processor Firmware

11. sTGC stage-0: L1A and readout (thru carrier). Stage-0 algorithm; time alignment

Enrique Kajomovitz Must (Department of Physics), Enrique Kajomovitz Must (Technion, Israel Institute of Technology)

5/6/20, 2:55 PM

Trigger Processor Firmware

12. Merge block, and output formatter to SL.

George Chatzianastasiou (University of Innsbruck (AT))

5/6/20, 3:25 PM

Trigger Processor Firmware

7. Results of combined tests with SL. Fixed latency. Latency measurements.

Lorne Levinson (Weizmann Institute of Science (IL))

5/6/20, 3:55 PM

Trigger Processor Firmware

3. Carrier v3 design.Validation/test results (Bucarest/Samway, standalone)

Andrei Scurtu (Samway SRL), Sorin Martoiu (Horia Hulubei National Institute of Physics and Nuclear Enginee)

5/6/20, 4:35 PM

4. Board test protocol and procedures (for series production); acceptance criteria

Ricardo Di Curzio Lera (University of Massachusetts (US)), Thiago Costa De Paiva (University of Massachusetts (US))

5/6/20, 5:00 PM

5. Production plan and schedule

Mihai Savu (Samway Electronic), Sorin Martoiu (Horia Hulubei National Institute of Physics and Nuclear Enginee)

5/6/20, 5:30 PM

6. Installation plans @ P1 and commissioning

Alexander Naip Tuna (Harvard University (US))

5/6/20, 6:05 PM

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