|
14:00
|
Review procedure
-
Hucheng Chen
(Brookhaven National Laboratory (US))
|
|
14:10
|
Introduction & Review Scope
-
Stephanie Ulrike Zimmermann
(Albert Ludwigs Universitaet Freiburg (DE))
|
|
14:20
|
Trigger Processor Firmware
(until 16:20)
|
|
14:25
|
Micromegas: L1A and readout (thru carrier). Algorithms and time alignment.
-
Thiago Costa De Paiva
(University of Massachusetts (US))
Nathan Felt
(Harvard University (US))
Nathan Felt
(Unknown)
|
|
14:55
|
sTGC stage-0: L1A and readout (thru carrier). Stage-0 algorithm; time alignment
-
Enrique Kajomovitz Must
(Department of Physics)
Enrique Kajomovitz Must
(Technion, Israel Institute of Technology)
|
|
15:25
|
Merge block, and output formatter to SL.
-
George Chatzianastasiou
(University of Innsbruck (AT))
|
|
15:55
|
Results of combined tests with SL. Fixed latency. Latency measurements.
-
Lorne Levinson
(Weizmann Institute of Science (IL))
|
|
16:20
|
--- Coffee break and rest from staring on a screen ---
|
|
16:35
|
Carrier v3 design.Validation/test results (Bucarest/Samway, standalone)
-
Sorin Martoiu
(Horia Hulubei National Institute of Physics and Nuclear Enginee)
Andrei Scurtu
(Samway SRL)
|
|
17:00
|
Board test protocol and procedures (for series production); acceptance criteria
-
Ricardo Di Curzio Lera
(University of Massachusetts (US))
Thiago Costa De Paiva
(University of Massachusetts (US))
|
|
17:30
|
Production plan and schedule
-
Sorin Martoiu
(Horia Hulubei National Institute of Physics and Nuclear Enginee)
Mihai Savu
(Samway Electronic)
|
|
18:05
|
Installation plans @ P1 and commissioning
-
Alexander Naip Tuna
(Harvard University (US))
|
