SoC Interest Group Meeting

Europe/Zurich
Videoconference
SoC Interest Group Meeting
Zoom Meeting ID
69605808118
Host
Ralf Spiwoks
Passcode
27409485
Useful links
Join via phone
Zoom URL
    • 3:00 PM 3:10 PM
      Introduction 10m
      Speaker: Ralf Spiwoks (CERN)
    • 3:10 PM 3:35 PM
      Hardware/software co-simulation of the Zynq SoC of the CROME Measurement and Processing Unit 25m

      ZynQemu (Project name might change) is a project tackling HW-/SW Co-Simulation of the Zynq SoC. It uses QEMU as an emulator for the PS (ARM Cortex-A9) and QuestaSim for RTL simulation of the PL. The bridge between those simulators is based on libsystemctlm-soc, a Xilinx developed protocol for communication between SystemC and QEMU. It is able to connect all Zynq AXI buses as well as GPIO and Interrupts. Other peripherals and interfaces are not implemented so far. The project simplifies debugging and developing on the Zynq platform because of the visibility of all relevant signals and also enables verification using simulation. Currently it is developed for system-level simulation of the CROME Measurement and Processing Unit (CMPU) using a Zynq-7020 but can potentially be applied to other projects as well.

      Speaker: Jonas Bodingbauer (Vienna University of Technology (AT))
    • 3:40 PM 4:05 PM
      Zynq MPSoC for beam profile monitoring at the CERN accelerators 25m

      A new generation of beam profile monitors based on the ionisation of residual gas has been developed for the CERN Proton Synchrotron (PS) which is using Timepix3 hybrid pixel detectors. This enables direction detection of ionisation electrons inside the primary vacuum of the accelerator and a purely digital readout chain from the front-end in the tunnel to the back-end outside. The current readout is based on a Xilinx Virtex-7 FPGA that acts as an event buffer with trigger control and some limited beam profile processing.
      A consolidation project will bring this type of beam profile monitor to the Super Proton Synchrotron (SPS). The readout will be upgraded to a Zynq MPSoC platform to enable more processing in the readout hardware by taking advantage of the hard core processors.
      This presentation will first give an overview of the operating principle of this type of beam profile monitors and how the current readout chain and processing works. After this, the next MPSoC-based implementation will be discussed.

      Speaker: Hampus Sandberg (CERN)
    • 4:10 PM 4:35 PM
      SPEC7, a versatile White Rabbit Node 25m

      SPEC7 is a candidate for successor of the well-known SPEC. It is based on a ZYNQ-7000 SoC that contains Programmable Logic (PL) and a Processing System (PS). Like the SPEC, the SPEC7 can operate stand-alone or in a PCIe slot and can carry an FMC module. The Processing System of the SPEC7 interfaces to Ethernet, USB, and SD-card and is capable of booting from any of these. Special attention was given to the SPEC7 design with respect to Low-Phase Noise.

      Speaker: Pascal Bos (Nikhef)
    • 4:40 PM 5:05 PM
      X2O ATCA board control solution 25m
      Speaker: Aleksei Greshilov (University of Florida (US))
    • 5:10 PM 5:20 PM
      ATLAS TDAQ SysAdmins - SoC status report 10m
      Speaker: Quentin Duponnois (CERN)