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26–30 Jun 2022
Riva del Garda, Italy
Europe/Rome timezone

Development of Timepix4 readout for experiments at synchrotrons and FELs

27 Jun 2022, 14:30
20m
Room Garda (Riva del Garda, Italy)

Room Garda

Riva del Garda, Italy

Riva del Garda Congress Centre Loc. Parco Lido 1 I - 38066 Riva del Garda (TN)
Oral Front End

Speaker

Alexandr Ignatenko

Description

Timepix4 is a versatile readout chip with 55 µm pixels, developed by CERN on behalf of the Medipix4 collaboration. Detector group at Deutsches Elektronen-Synchrotron (DESY) develops readout systems for the Timepix4 chip that can be used for experiments at modern synchrotrons and free-electron lasers (FELs). Timepix4 has two operating modes. Detectors with this chip operated in photon counting mode are able to replace detectors carrying the Medipix3 readout chip like LAMBDA in their existing applications. Applications like small-angle/wide-angle X-ray scattering (SAXS/WAXS), as well as powder diffraction can benefit from a 10 times higher count rate capability of Timepix4. When operated in the event-by event mode, Timepix4 can replace its predecessor Timepix3. Techniques for X-ray scattering experiments using correlation analysis will benefit the most of the ns time resolution. For instance, it will enable time-resolved experiments with single-bunch time resolution at the PETRA IV Storage Ring Facility. Timestamping is also useful in pump-probe experiments carried out at synchrotrons and FELs.
The development of Timepix4 readout boards is ongoing at DESY. A carrier board for a single chip has been designed, produced and tested. The layout of the board and the position of the chip at the edge of it allows for 2-chip tiled systems. For this first iteration, a commercially available readout board hosting a powerful Zynq UltraScale+ System on Chip has been chosen. Data is transferred to a control PC over Firefly optical links. This device is able to deal with the high readout bandwidth of the chip. Chip testing, as well as firmware and software developments are currently in progress.
The next step is development of multi-chip modules. New custom readout boards carrying 3 chips are currently under design. In the long term, multi-megapixel systems composed of multi-chip modules will be developed.

Primary authors

Presentation materials